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* etnaviv: use the correct uniform dirty bitsChristian Gmeiner2019-05-241-2/+2
* st/dri: enable EGL_ANDROID_blob_cache on gallium driversTapani Pälli2019-05-241-0/+29
* panfrost: Remove the standalone compilerAlyssa Rosenzweig2019-05-242-165/+0
* iris: Advertise coherent framebuffer fetchesKenneth Graunke2019-05-231-0/+2
* gallium: Add PIPE_CAP_FBFETCH_COHERENT and expose extensionsKenneth Graunke2019-05-233-0/+4
* gallium: Change PIPE_CAP_TGSI_FS_FBFETCH bool to PIPE_CAP_FBFETCH countKenneth Graunke2019-05-2319-22/+26
* iris: Record state sizes for INTEL_DEBUG=bat decoding.Kenneth Graunke2019-05-237-5/+57
* virgl: track valid buffer range for transfer syncChia-I Wu2019-05-227-20/+59
* virgl: remove support for buffer surfacesChia-I Wu2019-05-222-19/+15
* virgl: handle NULL shader resource explicitlyChia-I Wu2019-05-221-3/+3
* gallium: enable dmabuf on BSD as wellGreg V2019-05-221-1/+1
* iris: fix android buildTapani Pälli2019-05-221-0/+1
* etnaviv: fill missing offset in etna_resource_get_handlePhilipp Zabel2019-05-221-0/+1
* iris: Fix ALT mode regressions from shader cacheKenneth Graunke2019-05-212-4/+9
* radeonsi: fix a regression in si_rebind_bufferMarek Olšák2019-05-211-4/+8
* iris: Expose the disk cache to the state tracker as well.Kenneth Graunke2019-05-211-0/+8
* iris: Cache assembly shaders in the on-disk shader cacheDylan Baker2019-05-213-6/+236
* iris: Serialize the NIR to a blob we can use for shader cache purposes.Kenneth Graunke2019-05-212-0/+25
* iris: Start wiring up on-disk shader cacheDylan Baker2019-05-214-0/+81
* iris: Move iris_uncompiled_shader definition to iris_context.hKenneth Graunke2019-05-212-23/+23
* freedreno/a6xx: WFI in program stateobj tooRob Clark2019-05-201-0/+2
* freedreno/a6xx: make sure binning pass constlen is large enoughRob Clark2019-05-201-0/+13
* freedreno/a6xx: limit IBO state to draw passRob Clark2019-05-201-1/+1
* freedreno/a6xx: don't evaluate FS tex state in binning passRob Clark2019-05-202-6/+14
* lima/gpir: switch to use nir_lower_viewport_transformQiang Yu2019-05-204-101/+11
* lima/gpir: support vector ssa loadQiang Yu2019-05-202-5/+46
* lima/gpir: add helper function for emit load nodeQiang Yu2019-05-201-20/+19
* panfrost/midgard: Split up midgard_compile.c (RA)Alyssa Rosenzweig2019-05-1911-928/+1149
* panfrost: Improve fixed-function blendingAlyssa Rosenzweig2019-05-192-978/+34
* panfrost: Wire up nir_lower_blendAlyssa Rosenzweig2019-05-191-14/+33
* panfrost/midgard: Route new blending intrinsicsAlyssa Rosenzweig2019-05-191-106/+117
* panfrost/nir: Add nir_lower_blend passAlyssa Rosenzweig2019-05-194-1/+305
* panfrost: Fix Bifrost-specific paddingAlyssa Rosenzweig2019-05-191-7/+1
* panfrost: Cleanup panfrost_job commentsAlyssa Rosenzweig2019-05-191-6/+3
* panfrost/decode: Decode blend constantAlyssa Rosenzweig2019-05-192-2/+31
* panfrost: Hoist blend constant into Midgard-specific structAlyssa Rosenzweig2019-05-196-16/+21
* panfrost/decode: Disassemble Bifrost shadersAlyssa Rosenzweig2019-05-192-8/+10
* meson: expose glapi through osmesaEric Engestrom2019-05-181-2/+2
* draw: fix memory leak introduced 7720ce32aNeha Bhende2019-05-171-1/+3
* panfrost/midgard: TypofixAlyssa Rosenzweig2019-05-171-1/+1
* svga: Add an environment variable to force coherent surface memoryThomas Hellstrom2019-05-179-31/+82
* pipebuffer, winsys/svga: Add functionality to update pb_validate_entry flagsThomas Hellstrom2019-05-173-27/+33
* svga: Set the rendered-to flag for dma transfers to surfacesThomas Hellstrom2019-05-171-0/+4
* winsys/svga: Fix RELOC_INTERNAL mob GPU accessThomas Hellstrom2019-05-171-1/+9
* svga: Remove the surface_invalidate winsys functionThomas Hellstrom2019-05-176-31/+12
* Revert "softpipe/buffer: load only as many components as the the buffer resou...Gert Wollny2019-05-171-5/+2
* panfrost: Cleanup leak todosAlyssa Rosenzweig2019-05-173-16/+9
* panfrost: assert(0) -> unreachable for some switchAlyssa Rosenzweig2019-05-162-31/+18
* freedreno: Log the number of loops in the shader for shader-db.Eric Anholt2019-05-161-2/+2
* freedreno: Output the same shader-db format as v3d and intel.Eric Anholt2019-05-161-15/+4
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