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* radeonsi: update dirty_level_mask before dispatchingSamuel Pitoiset2017-08-302-0/+6
| | | | | | | | | This fixes a rendering issue with Hitman when bindless textures are enabled. Fixes: 2263610827 ("radeonsi: flush DB caches only when transitioning from DB to texturing") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* llvmpipe: initialize llvmpipe->dirty with LP_NEW_SCISSORBrian Paul2017-08-291-0/+6
| | | | | | | | | | | | | | If llvmpipe_set_scissor_states() is never called, we still need to be sure that derived scissor/clip state is updated. As of commit 743ad599a97d09b1 that function might not be called. Fixes regressed Piglit gl-1.0-scissor-offscreen -fbo -auto test. Reviewed-by: Roland Scheidegger <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101709 Fixes: 743ad599a97 ("st/mesa: don't set 16 scissors and 16 viewports if they're unused") Cc: "17.2" <[email protected]>
* ac/debug: Support multiple trace ids for nested IBs.Bas Nieuwenhuizen2017-08-291-9/+10
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radeonsi: stop leaking nirTimothy Arceri2017-08-291-0/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: rewrite late alloc VS limit computationMarek Olšák2017-08-281-12/+25
| | | | | | This is still very simple, but it's better than before. Loosely ported from Vulkan.
* gallium/radeon: set EVENT_WRITE_EOP.INT_SEL = wait for write confirmationMarek Olšák2017-08-281-3/+9
| | | | | | | Ported from Vulkan. Not sure what this is good for.. maybe write confirmation from L2 flushes? Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/u_threaded: rename IGNORE_VALID_RANGE -> NO_INFER_UNSYNCHRONIZEDMarek Olšák2017-08-283-5/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/u_threaded: disallow discard_range if map_buffer is unsynchronizedMarek Olšák2017-08-281-1/+3
| | | | | | | The discard range codepath takes precedence, so if we get both unsynchronized and discard_range, choose unsynchronized. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: correct maximum wave count per SIMDMarek Olšák2017-08-281-1/+12
| | | | | | v2: don't special-case Tonga and Iceland. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/docs: Fix an inequality sign of TGSI_SEMANTIC_SUBGROUP_LT_MASKGwan-gyeong Mun2017-08-281-1/+1
| | | | | | | | | | | | | | A previous expression presents same as TGSI_SEMANTIC_SUBGROUP_GT_MASK. It fixes a direction of an inequality for TGSI_SEMANTIC_SUBGROUP_LT_MASK. before: bit index > TGSI_SEMANTIC_SUBGROUP_INVOCATION after: bit index < TGSI_SEMANTIC_SUBGROUP_INVOCATION Signed-off-by: Mun Gwan-gyeong <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/docs: fix a typoGwan-gyeong Mun2017-08-281-1/+1
| | | | | Signed-off-by: Mun Gwan-gyeong <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* i915g: Remove a few unused variablesEduardo Lima Mitev2017-08-281-16/+0
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* Revert "radeonsi: get the raster config from AMDGPU on SI"Marek Olšák2017-08-271-17/+0
| | | | | | | | | | | | This reverts commit fc99cb3c9edee3af773700cf7ebdc60dc02fcaba. "The performance went down from 64.7 to 51.4 fps in Valley and from 30.8 to 25.1 fps in Heaven on Radeon HD 7970. Other games seem to have also a 10-25% performance decrease." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102429 It looks like we can't use the raster config values from the kernel.
* etnaviv: use correct param for etna_compatible_rs_format(..)Christian Gmeiner2017-08-261-1/+1
| | | | | | | | | Found by code inspection. Fixes: c9e8b49b885 ("etnaviv: gallium driver for Vivante GPUs") Cc: [email protected] Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* gallium/vbuf: fix buffer reference bugsBrian Paul2017-08-251-4/+3
| | | | | | | | | | | | | | | | | | In two places we called pipe_resource_reference() to remove a reference to a vertex buffer resource. But we neglected to check if the buffer was a user buffer and not a pipe_resource. This caused us to pass an invalid pipe_resource pointer to pipe_resource_reference(). Instead of calling pipe_resource_reference(&vbuf->resource, NULL), use pipe_vertex_buffer_unreference(&vbuf) which checks the is_user_buffer field and does the right thing. Also, explicity set the is_user_buffer field to false after setting the vbuf->resource pointer to out_buffer. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102377 Reviewed-by: Marek Olšák <[email protected]> Tested-by: Bruce Cherniak <[email protected]>
* gallium/u_threaded: fix a typoMarek Olšák2017-08-251-1/+1
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* a2xx: fix DST_ALPHA blending for non-alpha formatsIlia Mirkin2017-08-253-5/+21
| | | | | | | | If we're rendering to a format without alpha, convert DST_ALPHA blend to a ONE so that factors are properly computed. This same workaround is done on a3xx+ as well. Signed-off-by: Ilia Mirkin <[email protected]>
* a2xx: set constant blend colorIlia Mirkin2017-08-251-0/+9
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* radeonsi: set IF_THRESHOLD to 4Timothy Arceri2017-08-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In 74e39de9324d it was set to 3 and it was reported that 4 caused tesseract to start spilling VGPRs. This no longer seems to be the case. Totals: SGPRS: 2787844 -> 2787764 (-0.00 %) VGPRS: 1713121 -> 1712717 (-0.02 %) Spilled SGPRs: 7532 -> 7532 (0.00 %) Spilled VGPRs: 49 -> 33 (-32.65 %) Private memory VGPRs: 2060 -> 2060 (0.00 %) Scratch size: 2200 -> 2180 (-0.91 %) dwords per thread Code Size: 79265520 -> 79248360 (-0.02 %) bytes LDS: 436 -> 436 (0.00 %) blocks Max Waves: 670535 -> 670608 (0.01 %) Wait states: 0 -> 0 (0.00 %) Before: VGPR SPILLING APPS Shaders SpillVGPR PrivVGPR ScratchSize EffectsCaveDemo 301 0 256 264 ReflectionsSubwayDemo 264 0 256 264 VehicleGame 295 0 128 132 bioshock-infinite 1140 0 448 516 dirt-showdown 453 33 0 28 gang-beasts 364 0 500 496 kerbal-space-program 1228 0 472 480 tomb-raider-ultra 1199 16 0 20 After: VGPR SPILLING APPS Shaders SpillVGPR PrivVGPR ScratchSize EffectsCaveDemo 301 0 256 264 ReflectionsSubwayDemo 264 0 256 264 VehicleGame 295 0 128 132 bioshock-infinite 1140 0 448 516 dirt-showdown 453 33 0 28 gang-beasts 364 0 500 496 kerbal-space-program 1228 0 472 480 The only change in VGPR spills is the elimination of all spills in Tomb Raider at Ultra settings. Closer examination shows that the shaders go over the limit because they contain three expressions a mul, rcp and ubo load. The ubo load is actually used elsewhere and is therefore stored in a temp already in IR such as tgsi but glsl ir counts it agaist the if cost. Acked-by: Nicolai Hähnle <[email protected]> Acked-by: Marek Olšák <[email protected]>
* glsl: pass shader source keys to the disk cacheTimothy Arceri2017-08-251-1/+1
| | | | | | | We don't actually write them to disk here. That will happen in the following commit. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: get the raster config from AMDGPU on SIMarek Olšák2017-08-241-0/+17
| | | | | | Not sure yet if we wanna do this on CIK and VI too. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clean up setting GRBM_GFX_INDEXMarek Olšák2017-08-241-19/+22
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move PA_SC_RASTER_CONFIG emission into a separate functionMarek Olšák2017-08-241-70/+73
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallivm: remove unused variableBrian Paul2017-08-241-2/+0
| | | | Trivial.
* pipe-loader: use MAYBE_UNUSED to silence warningBrian Paul2017-08-241-1/+2
| | | | Trivial.
* nv50/ir: properly set sType for TXF ops to U32Ilia Mirkin2017-08-241-0/+3
| | | | | | | | | | | | All of the coordinates and LOD args are integers for TXF. This mostly doesn't matter, except for converting into a levelZero=true operation by removing an explicit zero LOD. For the comparison against zero to work properly, the sType of the instruction has to be set correctly. Fixes: KHR-GL45.robust_buffer_access_behavior.texel_fetch Reported-by: Karol Herbst <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* st/va: exclude the buffer reallocation for encode caseLeo Liu2017-08-231-1/+1
| | | | | | | | | Since encoder only support de-interlaced buffers. v2: move to parameter call to tell dec/enc Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* swr: limit pipe_draw_info->restart_index usageTim Rowley2017-08-231-1/+4
| | | | | | | | Only copy this value when in restart drawing mode. Eliminates valgrind errors when running trivial programs. Reviewed-by: Bruce Cherniak <[email protected]>
* radeonsi: fix wrong assertion in si_init_bindless_descriptors()Samuel Pitoiset2017-08-231-1/+1
| | | | | | Bad mistake, sorry. Signed-off-by: Samuel Pitoiset <[email protected]>
* radeon/video: Return false explicitly for HEVC if not the caseLeo Liu2017-08-231-0/+1
| | | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/docs: Fix the math formula of U2I64Gwan-gyeong Mun2017-08-231-2/+2
| | | | | | | | | | | | | before: dst.xy = (uint64_t) src0.x dst.zw = (uint64_t) src0.y after: dst.xy = (int64_t) src0.x dst.zw = (int64_t) src0.y Signed-off-by: Mun Gwan-gyeong <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/docs: Add missing word "Not"Gwan-gyeong Mun2017-08-231-1/+1
| | | | | Signed-off-by: Mun Gwan-gyeong <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* tgsi: store opcode mnemonics in a separate tableNicolai Hähnle2017-08-232-6/+16
| | | | | | | | | | They are only used for debug info. Together with making tgsi_opcode_info::opcode a bitfield, this reduces the size of tgsi_opcode_info on 64-bit systems from 24 bytes to 4 bytes, and makes the whole data structure a bit more linker friendly. Reviewed-by: Marek Olšák <[email protected]>
* gallium: use tgsi_get_opcode_name instead of tgsi_opcode_info::mnemonicNicolai Hähnle2017-08-235-7/+10
| | | | Reviewed-by: Marek Olšák <[email protected]>
* tgsi: macro-ify the opcodes tableNicolai Hähnle2017-08-233-251/+263
| | | | | | | | | So we can easily re-arrange members of tgsi_opcode_info, and readers of the code don't have to guess what all the 0s mean. Mostly done with regex search&replace. Reviewed-by: Marek Olšák <[email protected]>
* tgsi: remove post_indent from some 64-bit opcodesNicolai Hähnle2017-08-231-6/+6
| | | | Reviewed-by: Marek Olšák <[email protected]>
* tgsi: reduce tgsi_opcode_info::pre_dedent and post_indent to 1 bitNicolai Hähnle2017-08-231-2/+2
| | | | | | | | It's not clear why they were ever 2 bits to begin with. Perhaps the original intent was to use signed values, but that doesn't seem to have ever been the case in master. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: fix saving multi-part command streamsNicolai Hähnle2017-08-231-1/+1
| | | | | | Use the correct type to fix pointer arithmetic. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: update comment describing indices into sctx->descriptorsNicolai Hähnle2017-08-231-6/+5
| | | | Reviewed-by: Marek Olšák <[email protected]>
* util: fix valgrind errors when dumping pipe_draw_infoNicolai Hähnle2017-08-231-3/+9
| | | | | | | Various index-related fields are only initialized when required, so they should only be dumped in those cases. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: do not assert when reserving bindless slot 0Samuel Pitoiset2017-08-231-1/+4
| | | | | | | | | When assertions were disabled, the compiler removed the call to util_idalloc_alloc() and the first allocated bindless slot was 0 which is invalid per the spec. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: rename some bindless-related helper functionsSamuel Pitoiset2017-08-231-21/+21
| | | | | | | I think it makes more sense. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: minor cleanups in si_make_{texture,image}_handle_resident()Samuel Pitoiset2017-08-231-12/+12
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* Android: gallium_dri: pass dri.sym to linkerRob Herring2017-08-221-0/+7
| | | | | | | | | | | | | | | | Pass the dri.sym version script to the linker. This ensures only explicitly exported symbols are exported and shrinks the library by up to 60KB. HAVE_DLADDR also needs to be set so that __driDriverExtensions is defined. We need to pass "--undefined-version" because the Android build system sets --no-undefined-version by default and we get an error on driver specific symbols if those drivers are disabled without the option. Suggested-by: Emil Velikov <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* st/va: enable P016 format i.e. reallocate buffer if format changedLeo Liu2017-08-221-0/+12
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vcn: enable P016 mode supportLeo Liu2017-08-221-7/+11
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vcn: correct target buffer pitch calculationLeo Liu2017-08-221-1/+1
| | | | | | | since the way should be as same as UVD Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* tgsi/scan: fix uses_doubleMarek Olšák2017-08-221-2/+8
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: remove TGSI opcode SCSMarek Olšák2017-08-2222-491/+14
| | | | | | | use COS+SIN instead. Reviewed-by: Roland Scheidegger <[email protected]> Acked-by: Jose Fonseca <[email protected]>
* gallium/u_blitter: don't use boolean, TRUE, FALSEMarek Olšák2017-08-222-73/+73
| | | | | | | v2: cherry-picked from the bigger patch series Reviewed-by: Nicolai Hähnle <[email protected]> (v1) Tested-by: Brian Paul <[email protected]>
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