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* Revert "intel/gen11+: Enable Hardware filtering of Semi-Pipelined State in WM"Kenneth Graunke2019-09-231-9/+0
* freedreno/a6xx: do streamout only in binning passRob Clark2019-09-232-13/+16
* freedreno/a6xx: fix binning pass vs. xfbRob Clark2019-09-231-3/+7
* freedreno/a6xx: un-open-code PC_PRIMITIVE_CNTL_1.PSIZERob Clark2019-09-231-1/+1
* tgsi_to_nir: fix 2-component system values like tess_level_inner_defaultMarek Olšák2019-09-231-1/+3
* tgsi_to_nir: fix masked out image loadsMarek Olšák2019-09-231-2/+1
* nv50/ir/nir: comparison of integer expressions of different signedness warningKarol Herbst2019-09-231-1/+1
* nv50/ir: fix unnecessary parentheses warningKarol Herbst2019-09-231-1/+1
* lima: remove partial clear support from pipe->clear()Erico Nunes2019-09-231-93/+5
* dEQP-GLES2.functional.buffer.write.use.index_array.* are passing now.Boris Brezillon2019-09-231-2/+0
* panfrost: Fix indexed drawsBoris Brezillon2019-09-231-1/+1
* clover/nir: fix compilation with g++-5.5 and maybe earlierKarol Herbst2019-09-231-10/+7
* lima: implement BO cacheVasily Khoruzhick2019-09-228-30/+212
* lima: use 0 to poll if BO is busy in lima_bo_wait()Vasily Khoruzhick2019-09-221-1/+7
* lima: move damage bound build to resourceQiang Yu2019-09-233-22/+41
* lima: don't use damage system when full damageQiang Yu2019-09-231-0/+14
* lima: implement EGL_KHR_partial_updateQiang Yu2019-09-235-65/+86
* lima: fix PLBU viewport configurationIcenowy Zheng2019-09-223-21/+21
* nvc0: expose spirv supportKarol Herbst2019-09-214-3/+26
* clover: add support for passing kernels as nir to the driverKarol Herbst2019-09-217-7/+246
* clover: prepare supporting multiple IRsKarol Herbst2019-09-213-6/+64
* clover: add support for drivers having no proper binary formatKarol Herbst2019-09-211-2/+3
* clover/functional: add id_equals helperKarol Herbst2019-09-211-0/+15
* rename pipe_llvm_program_header to pipe_binary_program_headerKarol Herbst2019-09-215-7/+7
* gallium: add blob field to pipe_llvm_program_headerKarol Herbst2019-09-214-8/+4
* clover/llvm: Add functions for compiling from source to SPIR-VPierre Moreau2019-09-213-17/+92
* clover/llvm: Add options for dumping SPIR-V binariesPierre Moreau2019-09-213-1/+37
* clover/spirv: Add functions for parsing arguments, linking programs, etc.Pierre Moreau2019-09-212-5/+608
* clover/spirv: Add functions for validating SPIR-V binariesPierre Moreau2019-09-214-1/+168
* meson: Check for SPIRV-Tools and llvm-spirvPierre Moreau2019-09-211-2/+7
* gallium/osmesa: Fix the inability to set no context as current.Hal Gentz2019-09-201-0/+5
* Move blob from compiler/ to util/Jason Ekstrand2019-09-191-1/+1
* docs: Update bug report URLs for the gitlab migrationAdam Jackson2019-09-191-1/+1
* iris: Skip double-disabling TCS/TES/GS after BLORP operationsKenneth Graunke2019-09-191-0/+17
* iris: Rework iris_update_draw_parameters to be more efficientKenneth Graunke2019-09-183-40/+56
* iris: Use state_refs for draw parameters.Kenneth Graunke2019-09-183-23/+21
* util/u_queue: track job size and limit the size of queue growthTimothy Arceri2019-09-195-6/+7
* freedreno/a6xx: Write multiple regs for SP_VS_OUT_REG and SP_VS_VPC_DST_REGKristian H. Kristensen2019-09-181-6/+5
* freedreno/a6xx: Share shader state constructor and destructorKristian H. Kristensen2019-09-186-190/+76
* freedreno/a6xx: Track location of gl_Position out as we link itKristian H. Kristensen2019-09-181-3/+5
* iris: Avoid uploading SURFACE_STATE descriptors for UBOs if possibleKenneth Graunke2019-09-183-17/+53
* iris: Track per-stage bind history, reduce work accordinglyKenneth Graunke2019-09-184-6/+16
* iris: Don't flag IRIS_DIRTY_BINDINGS for constant usage historyKenneth Graunke2019-09-181-2/+1
* iris: Explicitly emit 3DSTATE_BTP_XS on Gen9 with DIRTY_CONSTANTS_XSKenneth Graunke2019-09-181-1/+6
* iris: Flag IRIS_DIRTY_BINDINGS_XS on constant buffer rebindsKenneth Graunke2019-09-181-1/+2
* radeonsi: include drm_fourcc.h to fix the buildMarek Olšák2019-09-181-0/+1
* radeonsi: implement pipe_screen::resource_get_paramMarek Olšák2019-09-181-22/+78
* gallium: extend resource_get_param to be as capable as resource_get_handleMarek Olšák2019-09-187-16/+56
* ac: move ac_get_num_physical_vgprs into radeon_infoMarek Olšák2019-09-181-3/+3
* ac: move ac_get_num_physical_sgprs into radeon_infoMarek Olšák2019-09-181-2/+2
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