summaryrefslogtreecommitdiffstats
path: root/src/gallium
Commit message (Collapse)AuthorAgeFilesLines
* vc4: Add support for depth clears and tests within a tile.Eric Anholt2014-08-1110-12/+65
| | | | | | | | | This doesn't load/store the Z contents across submits yet. It also disables early Z, since it's going to require tracking of Z functions across multiple state updates to track the early Z direction and whether it can be used. v2: Move the key setup to before the search for the key.
* vc4: Avoid flushing when mapping buffers that aren't in the batch.Eric Anholt2014-08-113-1/+50
| | | | | This should prevent a bunch of unnecessary flushes for things like updating immediate vertex data.
* vc4: Drop the flush at the end of the drawEric Anholt2014-08-112-2/+2
| | | | Now we actally get multiple draw calls per submit.
* vc4: Align following shader recs to 16 bytes.Eric Anholt2014-08-112-2/+10
| | | | | Otherwise, the low address bits will end up being interpreted as attribute counts.
* vc4: Fix a potential src buffer overflow in shader rec validation.Eric Anholt2014-08-111-0/+1
|
* vc4: Keep a reference to BOs queued for rendering.Eric Anholt2014-08-113-8/+4
| | | | | | Otherwise, once we're not flushing at the end of every draw, we'll free things like gallium resources, and free the backing GEM object, before we've flushed the rendering using it to the kernel.
* vc4: Compute the proper end address of the relocated command lists.Eric Anholt2014-08-112-2/+5
| | | | | | | | | render_cl_size/bin_cl_size includes relocations, while the hardware buffer doesn't. If you don't emit a HALT packet, the command parser continues until the end register's value. We can't allow executing unvalidated buffer contents (and it's actually harmful in the render lists Mesa is emitting, since VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF doesn't trigger a halt).
* vc4: Walk tiles horizontally, then vertically.Eric Anholt2014-08-111-2/+2
| | | | | I was confused looking at my addresses in dumps because I was seeing the tile branch offsets jumping all over.
* vc4: Track clears veresus uncleared draws, and the clear color.Eric Anholt2014-08-113-34/+117
| | | | | | This is a step toward queueing more than one draw per frame. Fixes piglit attribute0 test, since we get a working clear color now.
* vc4: Move the rest of RCL setup to flush time.Eric Anholt2014-08-112-33/+30
| | | | | We only want to set up render target config and clear colors once per frame.
* vc4: Move render command list calls to vc4_flush()Eric Anholt2014-08-112-40/+43
|
* vc4: Move bin command list ending commands to vc4_flush()Eric Anholt2014-08-112-4/+4
|
* vc4: Rename fields in the kernel interface.Eric Anholt2014-08-113-32/+32
| | | | | I decided I didn't like "len" compared to "size", and I keep typing shader_rec instead of shader_record[s] elsewhere, so make it consistent.
* vc4: Fix things to validate more than one shader state in a submit.Eric Anholt2014-08-113-67/+78
|
* vc4: Rewrite the kernel ABI to support texture uniform relocation.Eric Anholt2014-08-1110-97/+608
| | | | | | | | | | This required building a shader parser that would walk the program to find where the texturing-related uniforms are in the uniforms stream. Note that as of this commit, a new kernel is required for rendering on actual VC4 hardware (currently that commit is named "drm/vc4: Introduce shader validation and better command stream validation.", but is likely to be squashed as part of an eventual merge of the kernel driver).
* vc4: Add docs for the drm interfaceEric Anholt2014-08-111-9/+61
|
* vc4: Add load/store to the validatorEric Anholt2014-08-111-11/+9
|
* vc4: Switch simulator to using kernel validatorEric Anholt2014-08-1111-62/+840
| | | | | | | | This ensures that when I'm using the simulator, I get a closer match to what behavior on real hardware will be. It lets me rapidly iterate on the kernel validation code (which otherwise has a several-minute turnaround time), and helps catch buffer overflow bugs in the userspace driver faster.
* vc4: Drop pointless shader state structEric Anholt2014-08-112-14/+10
|
* vc4: Add support for texture rectanglesEric Anholt2014-08-112-0/+42
| | | | v2: Rebase on helpers change.
* vc4: Add support for texturing (under simulation)Eric Anholt2014-08-118-13/+277
| | | | | | | | Only rgba8888 works, and only a single texture unit, and it's only under simulation because I haven't built the kernel interface yet. v2: Rebase on helpers. v3: Fold in the don't-break-the-arm-build fix.
* vc4: Drop PIPE_SHADER_CAP_MAX_ADDRSEric Anholt2014-08-111-2/+0
| | | | Fixes the build since c10332bbb8889d733bdaa729ef23cbd90176b55d
* gallium: remove PIPE_SHADER_CAP_MAX_ADDRSMarek Olšák2014-08-1115-35/+0
| | | | | | | | | | | | | | | This limit is fixed in Mesa core and cannot be changed. It only affects ARB_vertex_program and ARB_fragment_program. The minimum value for ARB_vertex_program is 1 according to the spec. The maximum value for ARB_vertex_program is limited to 1 by Mesa core. The value should be zero for ARB_fragment_program, because it doesn't support ARL. Finally, drivers shouldn't mess with these values arbitrarily. Reviewed-by: Ilia Mirkin <[email protected]>
* gallium: pass st_config_options to query_versionsMarek Olšák2014-08-115-23/+29
| | | | | | | So move it from dri_context to dri_screen. This will be needed for version computations. Reviewed-by: Ilia Mirkin <[email protected]>
* gallium/stapi: move setting GL versions to the state trackerMarek Olšák2014-08-113-12/+25
| | | | | | | All flags are set for st/mesa, so the state tracker doesn't have to check them. Reviewed-by: Ilia Mirkin <[email protected]>
* gallium/radeon: Set gpu_address to 0 if r600_virtual_address is falseNiels Ole Salscheider2014-08-101-0/+2
| | | | | | | | | | | Without this patch I get the following during DMA transfers: [drm:radeon_cs_ib_chunk] *ERROR* Invalid command stream ! radeon 0000:01:00.0: CP DMA dst buffer too small (21475829792 4096) This is a fixup for e878e154cdfd4dbb5474f776e0a6d86fcb983098. Signed-off-by: Niels Ole Salscheider <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: simplify constant buffer upload for big endianMarek Olšák2014-08-101-18/+4
| | | | | | | | Point util_memcpy_cpu_to_le32 to a buffer storage directly. v2: simplify more Reviewed-by: Michel Dänzer <[email protected]>
* winsys/radeon: fix compile warningsMarek Olšák2014-08-091-3/+4
|
* r600g/compute: fix compile warningsMarek Olšák2014-08-092-10/+11
| | | | Trivial.
* r300g: handle new shader capsMarek Olšák2014-08-091-0/+2
| | | | Trivial.
* radeonsi: fix CMASK and HTILE allocation on TahitiMarek Olšák2014-08-092-3/+56
| | | | | | | | | | | | | | | | Tahiti has 12 tile pipes, but P8 pipe config. It looks like there is no way to get the pipe config except for reading GB_TILE_MODE. The TILING_CONFIG ioctl doesn't return more than 8 pipes, so we can't use that for Hawaii. This fixes a regression caused by 9b046474c95f15338d4c748df9b62871bba6f36f on Tahiti. v2: add an assertion and print an error on failure Cc: [email protected] Reviewed-by: Michel Dänzer <[email protected]>
* gallium/radeon: remove r600_resource_vaMarek Olšák2014-08-091-9/+0
| | | | | Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: use gpu_address from r600_resourceMarek Olšák2014-08-093-21/+14
| | | | | Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: use gpu_address from r600_resourceMarek Olšák2014-08-095-39/+29
| | | | | Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: use gpu_address from r600_resourceMarek Olšák2014-08-096-56/+41
| | | | | Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: store VM address in r600_resourceMarek Olšák2014-08-093-2/+7
| | | | | | | This will help to get rid of the buffer_get_virtual_address calls. Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* r600g: remove useless r600_resource_va callsMarek Olšák2014-08-091-18/+9
| | | | | | | R600-R700 don't support virtual memory. Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: always prefer SWITCH_ON_EOP(0) on CIKMarek Olšák2014-08-094-10/+46
| | | | | | | | | | | | | | The code is rewritten to take known constraints into account, while always using 0 by default. This should improve performance for multi-SE parts in theory. A debug option is also added for easier debugging. (If there are hangs, use the option. If the hangs go away, you have found the problem.) Reviewed-by: Alex Deucher <[email protected]> v2: fix a typo, set max_se for evergreen GPUs according to the kernel driver
* radeonsi: fix a hang with instancing in Unigine Heaven/Valley on HawaiiMarek Olšák2014-08-091-5/+2
| | | | | | | | This isn't documented anywhere, but it's the only thing that works for this case. Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* vc4: Add support for the COS instruction.Eric Anholt2014-08-081-0/+38
|
* vc4: Add support for the SIN instruction.Eric Anholt2014-08-081-0/+35
| | | | v2: Rebase on helpers.
* vc4: Fix register aliasing for packing of scaled coordinates.Eric Anholt2014-08-081-11/+18
| | | | Fixes glean fragProg1's "ADD test" and likely many others.
* vc4: Add some debug code for forcing fragment shader output color.Eric Anholt2014-08-081-0/+15
|
* u_primconvert: Copy min/max_index from the original primitive.Eric Anholt2014-08-081-4/+2
| | | | | | | | | | | | | | | | | | These values are supposed to be the minimum/maximum index values used to read from the vertex buffers. This code either copies index values out of the old IB (so, same min/max as the original draw call), or generates a new IB (using index values between the start and the start + count of the old array draw info, which just happens to be what min/max_index are set to by st_draw.c). We were incorrectly setting the max_index in the converting-from-glDrawArrays case to the start vertex plus the number of vertices generated in the new IB, which broke QUADS primitive conversion on VC4 (where max_index really has to be correct, or the kernel might reject your draw call due to buffer overflow). Reviewed-by: Rob Clark <[email protected]> (from verbal description of the patch)
* vc4: Fix using and emitting the 1/W from the vertex/coord shaders.Eric Anholt2014-08-081-14/+20
| | | | v2: Rebase on helpers change.
* vc4: Add support for swizzles of 32 bit float vertex attributes.Eric Anholt2014-08-082-20/+73
| | | | | | | | | | | | Some tests start working (useprogram-flushverts, for example) due to getitng the right vertices now. Some that used to pass start failing with memory overflow during binning, which is weird (glsl-fs-texture2drect). And a couple stop rendering correctly (glsl-fs-bug25902). v2: Move the attribute format setup in the key from after search time to before the search. v3: Fix reading of attributes other than position (I forgot to respect attr and stored everything in inputs 0-3, i.e. position).
* vc4: Add support for the TGSI FRC opcode.Eric Anholt2014-08-081-0/+18
| | | | v2: Rebase on helpers.
* vc4: Add support for the TGSI TRUNC opcode.Eric Anholt2014-08-084-0/+15
| | | | v2: Rebase on helpers.
* vc4: Crank up the tile allocation BO sizeEric Anholt2014-08-081-2/+2
| | | | | This avoids a simulator assertion failure with glamor. I need to actually support resize, though.
* vc4: Add support for multiple attributesEric Anholt2014-08-084-69/+46
|
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 07:49:35 +0000