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* radeonsi: don't set RAW_WAIT for CP DMA clearsNicolai Hähnle2018-12-191-1/+2
* radeonsi/gfx9: use SET_UCONFIG_REG_INDEX packets when availableNicolai Hähnle2018-12-192-5/+15
* radeonsi: add si_init_draw_functions and make some functions staticNicolai Hähnle2018-12-194-22/+22
* radeonsi: extract declare_vs_blit_inputsNicolai Hähnle2018-12-191-18/+25
* radeonsi: move SI_FORCE_FAMILY functionality to winsysNicolai Hähnle2018-12-192-34/+36
* r600: remove redundant semicolonNicolai Hähnle2018-12-191-1/+1
* ddebug: always flush when requested, even when hang detection is disabledNicolai Hähnle2018-12-191-0/+2
* ddebug: simplify watchdog loop and fix crash in the no-timeout caseNicolai Hähnle2018-12-193-73/+52
* meson: add etnaviv to the tools optionChristian Gmeiner2018-12-181-1/+2
* st/dri: replace format conversion functions with single mapping tableLucas Stach2018-12-182-352/+149
* st/dri: allow both render and sampler compatible dma-buf formatsLucas Stach2018-12-181-12/+18
* etnaviv: use surface format directlyLucas Stach2018-12-182-9/+4
* nir/opt_peephole_select: Don't peephole_select expensive math instructionsIan Romanick2018-12-172-2/+2
* nir/opt_peephole_select: Don't try to remove flow control around indirect loadsIan Romanick2018-12-172-2/+2
* vc4: Reuse nir_format_convert.h in our blend lowering.Eric Anholt2018-12-171-33/+3
* nir: Add a bool to int32 lowering passJason Ekstrand2018-12-162-0/+4
* nir: Rename Boolean-related opcodes to include 32 in the nameJason Ekstrand2018-12-162-30/+30
* nir/tgsi: Use nir_bany in ttn_kill_ifJason Ekstrand2018-12-161-3/+1
* vc4: Use the original bit size when scalarizing uniform loads.Eric Anholt2018-12-161-1/+2
* clover: Fix build after clang r348827Jan Vesely2018-12-161-1/+6
* v3d: Drop in a bunch of notes about performance improvement opportunities.Eric Anholt2018-12-142-1/+13
* v3d: Use the uniform pretty-printer in v3d_write_uniforms()'s debug code.Eric Anholt2018-12-141-1/+3
* v3d: Move uinfo->data[] dereference to the top of v3d_write_uniforms().Eric Anholt2018-12-141-15/+13
* v3d: Add support for draw indirect for GLES3.1.Eric Anholt2018-12-142-2/+31
* v3d: Add safety checks for resource_create().Eric Anholt2018-12-141-0/+6
* v3d: Add support for texturing from linear.Eric Anholt2018-12-146-3/+110
* v3d: Add support for using the TFU to do some blits.Eric Anholt2018-12-141-42/+129
* v3d: Don't forget to bump the number of writes when doing TFU ops.Eric Anholt2018-12-141-0/+2
* v3d: Set up the right stride for raster TFU.Eric Anholt2018-12-141-1/+1
* v3d: Don't forget to wait for our TFU job before rendering from it.Eric Anholt2018-12-141-0/+8
* nvc0: always keep TSC slot 0 bound to fix TXFIlia Mirkin2018-12-142-0/+21
* nvc0: replace use of explicit default_tsc with entry 0Ilia Mirkin2018-12-146-22/+25
* freedreno/a6xx: fix corrupted uniformsRob Clark2018-12-141-1/+2
* etnaviv: drop redundant ctx function parameterChristian Gmeiner2018-12-141-4/+3
* freedreno/a6xx: fix resource_copy_region()Rob Clark2018-12-131-9/+24
* freedreno: move fd_resource_copy_region()Rob Clark2018-12-133-62/+73
* freedreno/a6xx: more blitter fixesRob Clark2018-12-131-10/+22
* freedreno: update generated headersRob Clark2018-12-138-30/+39
* gallium/aux: add is_unorm() helperRob Clark2018-12-132-0/+24
* freedreno/a6xx: fix blitter crashRob Clark2018-12-131-0/+17
* freedreno: also set DUMP flag on shadersRob Clark2018-12-135-20/+22
* freedreno: debug GEM obj namesRob Clark2018-12-138-17/+19
* mesa/st: Expose compute shaders when NIR support is advertised.Eric Anholt2018-12-131-1/+2
* virgl: work around bad assumptions in virglrendererErik Faye-Lund2018-12-131-1/+32
* virgl: wrap vertex element state in a structErik Faye-Lund2018-12-132-9/+21
* virgl: simplify virgl_hw_set_index_bufferErik Faye-Lund2018-12-131-3/+2
* virgl: simplify virgl_hw_set_vertex_buffersErik Faye-Lund2018-12-131-4/+2
* meson: libfreedreno depends upon libdrm (for fence support)Rhys Kidd2018-12-121-3/+1
* virgl: force linear texturing supportErik Faye-Lund2018-12-121-2/+3
* gallivm: remove unused float coord wrapping for aos samplingRoland Scheidegger2018-12-121-507/+23
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