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* etnaviv: Reduce max offset to available hardware bits.Mathias Fröhlich2018-09-101-0/+2
| | | | | | Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* gallium: New cap PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET.Mathias Fröhlich2018-09-103-0/+6
| | | | | | | | | | | Introduce a new capability for the maximum value of pipe_vertex_element::src_offset. Initially just every driver backend returns the value previously set from _mesa_init_constants. So this shall end up in no functional change. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* virgl: don't send a shader create with no data. (v2)Dave Airlie2018-09-101-1/+1
| | | | | | | | | | | | | This fixes the situation where we'd send a shader with just the header and no data. piglit/glsl-max-varyings test was causing this to happen, and the renderer fix was breaking it. v2: drop fprintf Fixes: a8987b88ff1d "virgl: add driver for virtio-gpu 3D (v2)" Reviewed-by: Erik Faye-Lund <[email protected]>
* st/mesa: throttle texture uploads if their memory usage goes beyond a limitMarek Olšák2018-09-072-0/+137
| | | | | This prevents radeonsi from running out of memory. It also increases texture upload performance by being nice to the kernel memory manager.
* gallium: add PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGETMarek Olšák2018-09-0716-0/+24
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* Revert "gallium/os_thread: simplify helper pipe_current_thread_get_time_nano"Marek Olšák2018-09-071-1/+5
| | | | | | This reverts commit 6d477bc5460eec14c6a0d047a0384c9ce5c7609b. It fixes the Windows build hopefully.
* radeonsi: pin the winsys thread to the requested L3 cache (v2)Marek Olšák2018-09-074-0/+46
| | | | | | v2: rebase Reviewed-by: Brian Paul <[email protected]>
* gallium/u_threaded: implement set_context_param for thread pinning (v2)Marek Olšák2018-09-072-0/+41
| | | | | | | v2: - use set_context_param - set set_context_param even if the driver doesn't implement it Reviewed-by: Brian Paul <[email protected]>
* st/mesa: pin driver threads to a specific L3 cache on AMD Zen (v2)Marek Olšák2018-09-072-0/+46
| | | | | | v2: use set_context_param Reviewed-by: Brian Paul <[email protected]>
* gallium: add pipe_context::set_context_param for tuning perf on AMD Zen (v2)Marek Olšák2018-09-075-0/+59
| | | | | | | | | State trackers will not use the new param directly, but will instead use a helper in MakeCurrent that does the right thing. v2: rework the interface Reviewed-by: Brian Paul <[email protected]>
* gallium/os_thread: simplify helper pipe_current_thread_get_time_nanoMarek Olšák2018-09-071-5/+1
| | | | Reviewed-by: Brian Paul <[email protected]>
* gallium/u_cpu_detect: get the number of cores per L3 cache for AMD ZenMarek Olšák2018-09-072-0/+25
| | | | Reviewed-by: Brian Paul <[email protected]>
* gallium/u_cpu_detect: fix parsing the CPU familyMarek Olšák2018-09-071-1/+2
| | | | | | | | | | According to: https://support.amd.com/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf Also Intel: https://www.microbe.cz/docs/CPUID.pdf Reviewed-by: Brian Paul <[email protected]>
* gallium/u_cpu_detect: fix a race condition on initializationMarek Olšák2018-09-071-8/+10
| | | | Reviewed-by: Brian Paul <[email protected]>
* Replace uses of _mesa_bitcount with util_bitcountDylan Baker2018-09-073-8/+11
| | | | | | | | | | | | | and _mesa_bitcount_64 with util_bitcount_64. This fixes a build problem in nir for platforms that don't have popcount or popcountll, such as 32bit msvc. v2: - Fix additional uses of _mesa_bitcount added after this was originally written Acked-by: Eric Engestrom <[email protected]> (v1) Acked-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* move u_math to src/utilDylan Baker2018-09-0713-902/+9
| | | | | | | | | | | | | | | Currently we have two sets of functions for bit counts, one in gallium and one in core mesa. The ones in core mesa are header only in many cases, since they reduce to "#define _mesa_bitcount popcount", but they provide a fallback implementation. This is important because 32bit msvc doesn't have popcountll, just popcount; so when nir (for example) includes the core mesa header it doesn't (and shouldn't) link with core mesa. To fix this we'll promote the version out of gallium util, then replace the core mesa uses with the util version, since nir (and other non-core mesa users) can and do link with mesautils. Acked-by: Eric Engestrom <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* v3d: Fix setup of the VCM cache size.Eric Anholt2018-09-071-1/+1
| | | | | | | | | | | There were two bugs working together to make things mostly work: I wasn't dividing the VPM output size available by the size of a batch (vertex), but I also had the size of the VPM reduced by a factor of 8. Fixes dEQP-GLES3.functional.vertex_array_objects.all_attributes and it seems also my intermittent varying failures. Fixes: 1561e4984eb0 ("v3d: Emit the VCM_CACHE_SIZE packet.")
* v3d: Fix SRC_ALPHA_SATURATE blending for RTs without alpha.Eric Anholt2018-09-071-1/+3
| | | | | | | | Fixes dEQP-GLES3.functional.fragment_ops.blend.default_framebuffer.rgb_func_alpha_func.dst.src_alpha_saturate_src_alpha_saturate and friends with --deqp-egl-config-name=rgb565d0s0 Cc: "18.2" <[email protected]>
* freedreno: fix rast->depth_cleap_near/farRob Clark2018-09-071-1/+2
| | | | | Fixes: daa19363def gallium: split depth_clip into depth_clip_near & depth_clip_far Signed-off-by: Rob Clark <[email protected]>
* gallium: enable GL_AMD_depth_clamp_separate on r600, radeonsiMarek Olšák2018-09-0620-3/+23
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* gallium: split depth_clip into depth_clip_near & depth_clip_farMarek Olšák2018-09-0647-52/+92
| | | | for AMD_depth_clamp_separate.
* nir: Drop the vs_inputs_dual_locations optionJason Ekstrand2018-09-061-1/+0
| | | | | | | | | | | | | It was very inconsistently handled; the only things that made use of it were glsl_to_nir, glspirv, and nir_gather_info. In particular, nir_lower_io completely ignored it so anyone using nir_lower_io on 64-bit vertex attributes was going to be in for a shock. Also, as of the previous commit, it's set by every driver that supports 64-bit vertex attributes. There's no longer any reason to have it be an option so let's just delete it. Reviewed-by: Alejandro Piñeiro <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi/nir: Set vs_inputs_dual_locations and let NIR do the remapJason Ekstrand2018-09-061-0/+1
| | | | | | | | | | | | | | | | | We were going out of our way to disable dual-location re-mapping in NIR only to then do the remapping in st_glsl_to_nir.cpp. Presumably, this was so that double_inputs would be correct for the core state tracker. However, now that we've it to gl_program::DualSlotInputs which is unaffected by NIR lowering, we can let NIR lower things for us. The one tricky bit here is that we have to remap the inputs_read bitfield back to the single-slot convention for the gallium state tracker to use. Since radeonsi is the only NIR-capable gallium driver that also supports GL_ARB_vertex_attrib_64bit, we only have to worry about radeonsi when making core gallium state tracker changes. Acked-by: Marek Olšák <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* gallium: add PIPE_CAP_RASTERIZER_SUBPIXEL_BITSMarek Olšák2018-09-065-0/+8
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* freedreno/ir3: insert mov if same instruction in the outputs.Hyunjun Ko2018-09-051-0/+14
| | | | | | | | | | | | | | | | For example, result0 = texture(sampler[indexBase + 5], coords); result1 = texture(sampler[indexBase + 0], coords); result2 = texture(sampler[indexBase + 0], coords); out_result0 = result0; out_result1 = result1; out_result2 = result2; In this kind of case we need to insert an extra mov to the outputs so that the result could be assigned to each register respectively. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: make immediates array dynamicHyunjun Ko2018-09-053-1/+11
| | | | | | | | | | Since most shaders wouldn't need that large array of immediates, making the array dynamic could save unnecessary spaces. In addition, sometimes we can potentially have a much larger array of immediates to be lowered, which might be more than 64. Signed-off-by: Rob Clark <[email protected]>
* freedreno: allocate ctx's batch on demandRob Clark2018-09-054-15/+25
| | | | | | | Don't fall over when app wants more than 32 contexts. Instead allocate contexts on demand. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add fd_context_batch() accessorRob Clark2018-09-058-10/+21
| | | | | | | For cases in which (after the following commit) ctx->batch may be null. Prep work for following commit. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: fix mem2gmem for zsbufRob Clark2018-09-051-1/+4
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/batch: fix crash in !reorder caseRob Clark2018-09-051-2/+8
| | | | | | We aren't using the batch-cache if reorder==false. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: better compile_error() printingRob Clark2018-09-051-2/+16
| | | | | | Try to show the error at the appropriate line of nir Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: bordercolor fixesRob Clark2018-09-051-4/+25
| | | | | | | | | Port fixes from a5xx (f0715442) TODO maybe this should move to shared code, since it seems to be the same. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix context teardown harderRob Clark2018-09-054-8/+8
| | | | | | | | The border_color_uploaders need to be torn down before the transfer_pool is destroyed. Fixes: e11e9d63943 freedreno: fix context teardown race Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: ignore unused inputsRob Clark2018-09-051-1/+29
| | | | | | | | | | We could end up w/ inputs larger than vec4, simply because unused inputs are not split. Fixes things like dEQP-GLES31.functional.separate_shader.random.77 (and probably a handful of others) Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: fix debug build crashRob Clark2018-09-051-0/+7
| | | | | | Porting 0c8d9e923aa9239e20f9bc969faf9caa0b85237f to a6xx. Signed-off-by: Rob Clark <[email protected]>
* svga: rename face to layer_faceCharmaine Lee2018-09-051-22/+25
| | | | | Reviewed-by: Neha Bhende <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* svga: encode sample count in resource declarationsBrian Paul2018-09-054-0/+6
| | | | | | No regressions before the corresponding host-side change. Reviewed-by: Neha Bhende <[email protected]>
* svga: sync with upstream changes to surface flagsCharmaine Lee2018-09-059-14/+19
| | | | | | | | | SVGA device now supports 64 bits surface flags. This patch updates the winsys interface to allow 64 bits surface flags. The linux winsys layer will for now only honor the lower 32 bits of the surface flags. Reviewed-by: Brian Paul <[email protected]>
* svga: avoid try_blit() for some depth formats on non vgpu10.Neha Bhende2018-09-051-0/+13
| | | | | | | | | | | | | On non vgpu10, driver doesn't support util_blitter_blit for SVGA3D_Z_D16, SVGA3D_Z_D24x8, SVGA3D_Z_D24S8. Patch fixes following piglit tests regression on hwv8 caused by commit 27bf35caea5e: spec@arb_depth_texture@fbo-depth-gl-depth-component16-blit spec@arb_depth_texture@fbo-depth-gl-depth-component24-blit spec@arb_depth_texture@fbo-depth-gl-depth-component32-blit Tested with mtt-piglit on hw 8,9,10,11,13 and mtt-glretrace on windows and linux. Reviewed-by: Charmaine Lee <[email protected]>
* svga: convert dst format to linear when blending is enabled.Neha Bhende2018-09-051-1/+3
| | | | | | | | | | | When blending is enabled, framebuffer colorspace has to be linear. Previously, we never hit this case because we were not supporting sRGB drawable. Previous patch added that support. Tested with mtt glretrace, viewperf, piglit, conform. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* winsys/svga: Avoid cap2 code path for nowNeha Bhende2018-09-051-13/+5
| | | | | | | CAP2 functionality is not yet part of vmwgfx. This is causing unnecessary dmesg error messages. Reviewed-by: Charmaine Lee <[email protected]>
* svga: start using SVGA3dCmdIntraSurfaceCopy command for svga_blit.Neha Bhende2018-09-051-0/+112
| | | | | | | | | | | | | Basically, SVGA3dCmdIntraSurfaceCopy command allow copying when source and destination are same. Tested with MTT piglit, glretrace, viewperf, conform v2: changes as per Charmaine's comment v3: changes as per Charmaine's comment Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* svga/winsys: Add cap2 support in winsysNeha Bhende2018-09-054-2/+38
| | | | | Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* svga: Add SVGA3dCmdIntraSurfaceCopy command support in OpenGL driverNeha Bhende2018-09-053-0/+49
| | | | | | | v2: changes as per Charmaine's comment Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* svga: update device header files from upstreamBrian Paul2018-09-0515-196/+569
| | | | | | This is a squash commit of several earlier patches. Signed-off-by: Brian Paul <[email protected]>
* winsys/drm: Fix assert when try to accumulate an invalid fdCharmaine Lee2018-09-051-2/+7
| | | | | | | | | | This patch makes sure there is a valid fd before merging it to the context's fd in vmw_svga_winsys_fence_server_sync(). This fixes the assert running webot. No regression running kmscube. Reviewed-by: Sinclair Yeh <[email protected]>
* winsys/virgl/vtest: Correct off-by-one error in resource allocationGert Wollny2018-09-051-4/+9
| | | | | | | The resource bo array must already extended when the target index is equal to the current size of the array. Signed-off-by: Gert Wollny <[email protected]>
* winsys/virgl: Initialize value to silence valgrindGert Wollny2018-09-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | Silences: Conditional jump or move depends on uninitialised value(s) at 0xB72F2C0: virgl_drm_winsys_create (virgl_drm_winsys.c:854) by 0xB72F2C0: virgl_drm_screen_create (virgl_drm_winsys.c:926) by 0xB21C885: pipe_virgl_create_screen (drm_helper.h:275) by 0xB7201F0: pipe_loader_create_screen (pipe_loader.c:137) by 0xB639C91: dri2_init_screen (dri2.c:2112) by 0xB634F68: driCreateNewScreen2 (dri_util.c:153) by 0x63023E6: dri3_create_screen (dri3_glx.c:893) by 0x62D35BD: AllocAndFetchScreenConfigs (glxext.c:820) by 0x62D35BD: __glXInitialize (glxext.c:946) by 0x62CECB3: GetGLXPrivScreenConfig (glxcmds.c:174) by 0x62CF69C: glXQueryExtensionsString (glxcmds.c:1304) by 0x60AA7D9: ??? (in /usr/lib/x86_64-linux-gnu/libwaffle-1.so.0.5.2) by 0x4F81450: wfl_checked_display_connect (piglit-util-waffle.h:74) by 0x4F829E0: piglit_wfl_framework_init (piglit_wfl_framework.c:627) Signed-off-by: Gert Wollny <[email protected]>
* winsys/virgl: correct resource and handle allocation (v2)Gert Wollny2018-09-051-5/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes crash with piglit/bin/map_buffer_range-invalidate CopyBufferSubData \ increment-offset -auto -fbo * Resize the resource storage already when the count is equal to the allocated size, fixes: Invalid write of size 8 at 0xB72E4CF: virgl_drm_add_res (virgl_drm_winsys.c:629) by 0xB72E4CF: virgl_drm_emit_res (virgl_drm_winsys.c:663) by 0xB72A44A: virgl_encode_resource_copy_region (virgl_encode.c:776) by 0xB40CD12: st_copy_buffer_subdata (st_cb_bufferobjects.c:585) by 0xB244A3B: _mesa_CopyBufferSubData (bufferobj.c:2940) by 0x109A1E: upload (invalidate.c:169) by 0x109C2F: piglit_display (invalidate.c:215) by 0x4F80FBE: run_test (piglit_fbo_framework.c:52) by 0x4F66E5F: piglit_gl_test_run (piglit-framework-gl.c:229) by 0x10949D: main (invalidate.c:47) Address 0xbe07d30 is 0 bytes after a block of size 4,096 alloc'd at 0x4C31B25: calloc (in /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so) by 0xB72DAAF: virgl_drm_cmd_buf_create (virgl_drm_winsys.c:567) * Also resize the space allocated for the handles, fixes: Invalid write of size 4 at 0xB72E4F0: virgl_drm_add_res (virgl_drm_winsys.c:631) by 0xB72E4F0: virgl_drm_emit_res (virgl_drm_winsys.c:663) by 0xB72A44A: virgl_encode_resource_copy_region (virgl_encode.c:776) by 0xB40CD12: st_copy_buffer_subdata (st_cb_bufferobjects.c:585) by 0xB244A3B: _mesa_CopyBufferSubData (bufferobj.c:2940) by 0x109A1E: upload (invalidate.c:169) by 0x109C2F: piglit_display (invalidate.c:215) by 0x4F80FBE: run_test (piglit_fbo_framework.c:52) by 0x4F66E5F: piglit_gl_test_run (piglit-framework-gl.c:229) by 0x10949D: main (invalidate.c:47) Address 0xbe08570 is 0 bytes after a block of size 2,048 alloc'd at 0x4C2FB0F: malloc ( in /usr/lib/valgrind/vgpreload_memcheck-amd64- linux.so) by 0xB72DAC8: virgl_drm_cmd_buf_create (virgl_drm_winsys.c:572) Fixes: 4b15b5e803e ("virgl: resize resource bo allocation if we need to.") v2: - Use REALLOC macro and avoid memory leak when re-allocation fails - add Fixes tag (both Emil Velikov) - reorder commit message Signed-off-by: Gert Wollny <[email protected]>
* virgl: use hw-atomics instead of in-ssbo onesTomeu Vizoso2018-09-057-2/+89
| | | | | | | | Emulating atomics on top of ssbos can lead to too small max SSBO count, so let's use the hw-atomics mechanism to expose atomic buffers instead. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
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