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* radeonsi: Handle position input parameter for pixel shaders v2Tom Stellard2012-09-114-1/+53
* radeon/llvm: Coding style fixesTom Stellard2012-09-114-31/+31
* radeonsi: Move interpolation mode check into the compilerTom Stellard2012-09-112-12/+21
* radeonsi: Add missing interpolation mode to check for enabled modesTom Stellard2012-09-111-0/+1
* radeonsi: Pass shader type to the compilerTom Stellard2012-09-111-0/+12
* radeon/llvm: Add SHADER_TYPE instructionTom Stellard2012-09-118-1/+32
* r600g: avoid GPU doing constant preload from random addressJerome Glisse2012-09-112-0/+40
* radeonsi: Texture border colour fixes.Michel Dänzer2012-09-113-8/+56
* radeonsi: Handle NULL sampler states.Michel Dänzer2012-09-111-1/+1
* r600g: remove unused functionMarek Olšák2012-09-112-22/+0
* r600g: fix printf warningMarek Olšák2012-09-111-1/+2
* nvc0/ir: add initial code to support GK110 ISA encodingChristoph Bumiller2012-09-0710-13/+1691
* radeonsi: Float format fixups.Michel Dänzer2012-09-071-1/+24
* radeonsi: Handle more SNORM formats.Michel Dänzer2012-09-071-0/+22
* radeonsi: Handle TGSI_SEMANTIC_FOG.Michel Dänzer2012-09-071-0/+1
* radeon/llvm: Match fexp2 for SI.Michel Dänzer2012-09-071-1/+3
* r600g: order atom emission v3Jerome Glisse2012-09-067-82/+116
* r600g: fix num of dwords needed for alphatest_state atomJerome Glisse2012-09-061-1/+1
* llvmpipe: Make driver name more informative.José Fonseca2012-09-061-1/+4
* radeonsi: Handle more L/I/A format cases.Michel Dänzer2012-09-061-0/+14
* radeonsi: Enable whole quad mode for pixel shaders.Michel Dänzer2012-09-061-2/+10
* radeon/llvm: Add intrinsic for enabling whole quad mode in SI pixel shaders.Michel Dänzer2012-09-064-0/+23
* radeon/llvm: SI shader vector instructions implicitly use the EXEC register.Michel Dänzer2012-09-061-0/+4
* radeon/llvm: Extend SI EXEC register support.Michel Dänzer2012-09-062-2/+7
* radeon/llvm: Remove R600InstrInfo.td from TD_FILESTom Stellard2012-09-061-1/+0
* radeonsi: Enable NPOT textures again.Michel Dänzer2012-09-061-1/+1
* radeonsi: Mipmaps require memory footprint to be padded to powers of two.Michel Dänzer2012-09-061-0/+1
* radeonsi: Sampler view state simplification.Michel Dänzer2012-09-061-11/+9
* radeonsi: Untiled textures are linear aligned, not linear general.Michel Dänzer2012-09-061-3/+3
* radeon/llvm: Cleanup makefileTom Stellard2012-09-062-13/+37
* Remove useless checks for NULL before freeingMatt Turner2012-09-0528-115/+55
* Remove useless checks for NULL before freeingMatt Turner2012-09-058-31/+15
* Don't cast the return value of malloc/reallocMatt Turner2012-09-0510-20/+20
* Remove Xcalloc/Xmalloc/Xfree callsMatt Turner2012-09-058-27/+27
* Use the correct macro _WIN32 for Windows.Vinson Lee2012-09-055-6/+6
* radeon/llvm: Fix operand ordering for V_CNDMASK_B32Tom Stellard2012-09-051-3/+3
* radeon/llvm: Use correct float->int conversion opcode on SI.Tom Stellard2012-09-051-2/+4
* radeon/llvm: Fix lowering of SI_V_CNDLTTom Stellard2012-09-041-3/+3
* radeon/llvm: Fix encoding of V_CNDMASK_B32Tom Stellard2012-09-042-4/+4
* radeon/llvm: do not convert f32 operand of select_cc nodeVincent Lejeune2012-09-041-20/+20
* radeon/llvm: custom lowering for FP_TO_UINT when dst is i1 (bool)Vincent Lejeune2012-09-042-2/+26
* radeon/llvm: support setcc on f32Vincent Lejeune2012-09-041-9/+27
* radon/llvm: br_cc f32 now lowered without castVincent Lejeune2012-09-041-9/+24
* radeon/llvm: swap wrong OPCODE_IS_*_ZERO_* opcode and useVincent Lejeune2012-09-042-4/+4
* winsys/radeon: create only one winsys for each fdChristian König2012-09-042-2/+41
* radeonsi: stop big offsets from hanging the GPU v2Christian König2012-09-041-2/+9
* radeonsi: adjust PIPE_SHADER_CAP_MAX_CONSTSChristian König2012-09-042-5/+2
* radeon/llvm: fix SelectADDR8BitOffsetChristian König2012-09-041-1/+1
* gallivm,llvmpipe: Use 4-wide vectors on AMD Bulldozer.José Fonseca2012-09-043-1/+15
* r600g: adjust QUANT_MODE for higher precisionVadim Girlin2012-09-044-2/+24
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