| Commit message (Expand) | Author | Age | Files | Lines |
* | gallium: enable intel jitevents profiling | Tim Rowley | 2016-05-09 | 1 | -0/+9 |
* | swr: Add missing break in query switch statement. | Bruce Cherniak | 2016-05-09 | 1 | -0/+1 |
* | freedreno/ir3: allow for additional VS sysval inputs | Rob Clark | 2016-05-09 | 1 | -2/+5 |
* | r300g: add support for PIPE_FORMAT_x8R8G8B8_* | Marek Olšák | 2016-05-09 | 2 | -15/+77 |
* | radeonsi: fix undefined behavior (memcpy arguments must be non-NULL) | Nicolai Hähnle | 2016-05-07 | 1 | -1/+3 |
* | radeonsi: fix some reported undefined left-shifts | Nicolai Hähnle | 2016-05-07 | 1 | -3/+3 |
* | gallium/radeon: clean left-shift undefined behavior | Nicolai Hähnle | 2016-05-07 | 11 | -3989/+3989 |
* | gallium: fix various undefined left shifts into sign bit | Nicolai Hähnle | 2016-05-07 | 4 | -5/+5 |
* | radeonsi: Compute correct LDS size for fragment shaders. | Bas Nieuwenhuizen | 2016-05-06 | 1 | -3/+6 |
* | vc4: Add support for loading immediate values in QIR. | Eric Anholt | 2016-05-06 | 4 | -0/+32 |
* | vc4: Make vc4_qpu_validate() produce more verbose failures. | Eric Anholt | 2016-05-06 | 1 | -35/+71 |
* | vc4: Add a small QIR validate pass. | Eric Anholt | 2016-05-06 | 4 | -0/+127 |
* | vc4: Fix the src count on exp2/log2. | Eric Anholt | 2016-05-06 | 1 | -2/+2 |
* | vc4: Reuse QPU disasm's cond flags in QIR. | Eric Anholt | 2016-05-06 | 3 | -27/+46 |
* | vc4: When emitting an instruction to an existing temp, mark it non-SSA. | Eric Anholt | 2016-05-06 | 1 | -0/+2 |
* | vc4: Make sure that we don't overwrite the signal for PROG_END. | Eric Anholt | 2016-05-06 | 1 | -0/+8 |
* | nvc0: unreference images when the context is destroyed | Samuel Pitoiset | 2016-05-06 | 1 | -0/+4 |
* | radeonsi: set DECOMPRESS_Z_ON_FLUSH if nr_samples >= 4 | Marek Olšák | 2016-05-06 | 1 | -1/+2 |
* | r600g: use the hw MSAA resolving if formats are compatible | Marek Olšák | 2016-05-06 | 1 | -1/+2 |
* | st/omx/enc: fix incorrect reference picture order for B frames | Leo Liu | 2016-05-05 | 1 | -7/+12 |
* | vc4: fixup for new nir_foreach_block() | Connor Abbott | 2016-05-05 | 4 | -48/+20 |
* | ir3: fixup for new nir_foreach_block() | Connor Abbott | 2016-05-05 | 1 | -30/+21 |
* | swr: [rasterizer core] Faster modulo operator in ProcessVerts | Tim Rowley | 2016-05-05 | 1 | -1/+4 |
* | swr: [rasterizer] Small warning cleanup | Tim Rowley | 2016-05-05 | 2 | -8/+4 |
* | swr: [rasterizer] Add SWR_ASSUME / SWR_ASSUME_ASSERT macros | Tim Rowley | 2016-05-05 | 2 | -14/+52 |
* | swr: [rasterizer] Miscellaneous backend changes | Tim Rowley | 2016-05-05 | 3 | -22/+31 |
* | swr: [rasterizer] Add support for X24_TYPELESS_G8_UINT format | Tim Rowley | 2016-05-05 | 3 | -7/+41 |
* | swr: [rasterizer jitter] Fix printing bugs for tracing. | Tim Rowley | 2016-05-05 | 1 | -81/+24 |
* | swr: [rasterizer memory] Add missing store tiles function | Tim Rowley | 2016-05-05 | 1 | -1/+4 |
* | swr: [rasterizer jitter] Add asserts for supported formats in fetch shader | Tim Rowley | 2016-05-05 | 1 | -0/+2 |
* | swr: [rasterizer core] Fix thread allocation | Tim Rowley | 2016-05-05 | 1 | -17/+47 |
* | swr: [rasterizer core] Fix threadviz support in buckets | Tim Rowley | 2016-05-05 | 3 | -12/+14 |
* | swr: [rasterizer] Whitespace cleanup and misc changes | Tim Rowley | 2016-05-05 | 5 | -5/+2 |
* | radeonsi: mark descriptor loads as using dynamically uniform indices | Nicolai Hähnle | 2016-05-05 | 1 | -5/+17 |
* | swr: Remove stall waiting for core query counters. | Bruce Cherniak | 2016-05-05 | 4 | -124/+81 |
* | freedreno: remove null check before free | Thomas Hindoe Paaboel Andersen | 2016-05-05 | 1 | -2/+1 |
* | r600,compute: create vtx buffer for text + rodata | Jan Vesely | 2016-05-04 | 1 | -2/+10 |
* | freedreno: allow ctx->draw_vbo to fail | Rob Clark | 2016-05-04 | 5 | -30/+37 |
* | freedreno: move shader-stage dirty bits to global dirty flag | Rob Clark | 2016-05-04 | 8 | -59/+41 |
* | freedreno/a4xx: fix bogus offset for f32x24s8 stencil restore | Rob Clark | 2016-05-04 | 1 | -4/+5 |
* | freedreno: add some debug_asserts() to catch insane offsets | Rob Clark | 2016-05-04 | 1 | -0/+2 |
* | freedreno/a4xx: deal with VS which do not write position | Rob Clark | 2016-05-04 | 1 | -0/+7 |
* | freedreno/ir3: remove a couple redundant is_flow()s | Rob Clark | 2016-05-04 | 2 | -2/+2 |
* | freedreno/ir3: cp small negative integers too | Rob Clark | 2016-05-04 | 1 | -1/+2 |
* | freedreno/ir3: fix # of registers | Rob Clark | 2016-05-04 | 1 | -1/+1 |
* | freedreno/ir3: lower immeds to const | Rob Clark | 2016-05-04 | 3 | -4/+80 |
* | freedreno/ir3: add ir3_cp_ctx | Rob Clark | 2016-05-04 | 3 | -12/+22 |
* | nouveau/video: properly detect the decoder class for availability checks | Ilia Mirkin | 2016-05-04 | 1 | -8/+17 |
* | gallium/util: change assertion to conditional in util_bitmask_destroy() | Brian Paul | 2016-05-03 | 1 | -4/+4 |
* | cso: null-out previously bound sampler states | Brian Paul | 2016-05-03 | 1 | -1/+3 |