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* radeonsi/gfx9: pad shader binaries by 128 bytesMarek Olšák2017-03-301-0/+6
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: trivial shader and ring changesMarek Olšák2017-03-301-5/+15
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: sampler state changesMarek Olšák2017-03-301-1/+1
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: add a scissor bug workaroundMarek Olšák2017-03-301-0/+6
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: rasterizer changesMarek Olšák2017-03-301-2/+4
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: disable the 2-bit format fetch fixMarek Olšák2017-03-301-2/+6
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: set NUM_RECORDS correctlyMarek Olšák2017-03-303-3/+3
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: ELEMENT_SIZE changeMarek Olšák2017-03-302-7/+15
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: enable ETC2Marek Olšák2017-03-301-1/+2
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: disable RB+ on Vega10Marek Olšák2017-03-306-22/+39
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: init_config changesMarek Olšák2017-03-301-6/+32
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: don't set PA_SC_RASTER_CONFIG*Marek Olšák2017-03-301-15/+19
| | | | | | The registers don't exist on GFX9. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: Gather4 no longer needs the workaroundMarek Olšák2017-03-301-1/+2
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: CP DMA changesMarek Olšák2017-03-301-10/+30
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: query changes - EVENT_WRITE and SET_PREDICATIONMarek Olšák2017-03-301-10/+19
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: EVENT_WRITE_EOP -> RELEASE_MEMMarek Olšák2017-03-301-14/+25
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: INDIRECT_BUFFER changeMarek Olšák2017-03-301-1/+1
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: enable SDMA buffer copying & clearingMarek Olšák2017-03-301-3/+4
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: handle GFX9 in a few placesMarek Olšák2017-03-304-2/+5
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: don't read back non-existent SRBM registersMarek Olšák2017-03-301-3/+5
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: add IB parser supportMarek Olšák2017-03-301-0/+1
| | | | | | | | | Both GFX6 and GFX9 fields are printed next to each other in parsed IBs. The Python script parses both headers like one stream and tries to merge all definitions. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: set the LLVM processor, require LLVM 5.0Marek Olšák2017-03-302-0/+9
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi/gfx9: add GFX9 and VEGA10 enumsMarek Olšák2017-03-303-2/+10
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* amd: GFX9 packet changesMarek Olšák2017-03-301-2/+2
| | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* amd: add texture format definitions for GFX9Marek Olšák2017-03-301-4/+4
| | | | | | | | the DATA_FORMAT and NUM_FORMAT fields are the same, but some of the enums differ, thus add GFX6 and GFX9 suffixes, so that the IB parser can show enums for both. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* amd: resolve remaining definition conflicts with gfx9d.hMarek Olšák2017-03-302-3/+3
| | | | | | | | Add _GFX6 and _GFX9 suffixes to conflicting definitions. sid.h and gfx9d.h can now be included in the same file. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* amd: normalize register definition formattingMarek Olšák2017-03-301-15/+45
| | | | | | | This resolves trivial conflicts with gfx9d.h caused by different formatting. Some fields are also renamed. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* radeonsi: code shuffling in si_init_depth_surfaceMarek Olšák2017-03-301-54/+32
| | | | | | | use fewer local variables, re-order the assignments, so that the GFX9 diff is smaller here. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
* amdgpu/addrlib: Rewrite tile mode optmization codeXavi Zhang2017-03-301-7/+5
| | | | Note: remove reference to degrade4Space and use opt4Space instead.
* swr: [scons] Fix windows buildGeorge Kyriazis2017-03-291-7/+31
| | | | | | | | | | Fix codegen build break that was introduced earlier v2: update rules for gen_knobs.cpp and gen_knobs.h v3: Introduce bldroot and revert generator file changes, making patch simpler. Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
* r600g: check NULL return from r600_aligned_buffer_createJulien Isorce2017-03-281-0/+10
| | | | | Signed-off-by: Julien Isorce <jisorce@oblong.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* si_compute: check NULL return from u_upload_allocJulien Isorce2017-03-281-3/+11
| | | | | Signed-off-by: Julien Isorce <jisorce@oblong.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* r600g: check NULL return from u_upload_allocJulien Isorce2017-03-281-0/+4
| | | | | | | | | | | | | | Like done in si_state_draw.c::si_draw_vbo u_upload_alloc can fail, i.e. set output param *ptr to NULL, for 2 reasons: alloc fails or map fails. For both there is already a fprintf/stderr in radeon_create_bo and radeon_bo_do_map. In src/gallium/drivers/ it is a common usage to just avoid to crash by doing a silent check. But defer fprintf where the error comes from, libdrm calls. Signed-off-by: Julien Isorce <jisorce@oblong.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* swr: fix llvm-5.0.0 build bustageTim Rowley2017-03-281-9/+15
| | | | | | | Handle rename of llvm AttributeSet to AttributeList in the same fashion as ac_llvm_helper.cpp. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
* swr: [rasterizer jitter] fix llvm-5.0.0 build bustageTim Rowley2017-03-281-4/+3
| | | | | | Add CreateAlignmentAssumptionHelper to gen_llvm_ir_macros.py ignore list. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
* swr: [rasterizer core] Disable inline function expansionTim Rowley2017-03-281-0/+12
| | | | | | Disable expansion in windows Debug builds. Reviewed-by: George Kyriazis <george.kyriazis@intel.com>
* swr: [rasterizer common] Use C++ thread_local keywordTim Rowley2017-03-281-2/+2
| | | | | | Allows use of thread_local objects with constructors. Reviewed-by: George Kyriazis <george.kyriazis@intel.com>
* swr: [rasterizer core] SIMD16 Frontend WIPTim Rowley2017-03-288-81/+371
| | | | | | Implement widened clipper and binner interfaces for SIMD16. Reviewed-by: George Kyriazis <george.kyriazis@intel.com>
* swr: [rasterizer core] Don't bind single-threaded contextsTim Rowley2017-03-281-1/+1
| | | | Reviewed-by: George Kyriazis <george.kyriazis@intel.com>
* swr: [rasterizer core] Enable SIMD16Tim Rowley2017-03-283-8/+20
| | | | | | Make the AVX512 insert/extract intrinsics KNL-compatible Reviewed-by: George Kyriazis <george.kyriazis@intel.com>
* swr: [rasterizer jitter] Clean up EngineBuilder constructionTim Rowley2017-03-281-7/+5
| | | | Reviewed-by: George Kyriazis <george.kyriazis@intel.com>
* swr: [rasterizer codegen] add cmdline to archrast gen filesTim Rowley2017-03-285-2/+18
| | | | Reviewed-by: George Kyriazis <george.kyriazis@intel.com>
* swr: [rasterizer core] SIMD16 Frontend WIPTim Rowley2017-03-282-22/+136
| | | | | | Fix GS and streamout. Reviewed-by: George Kyriazis <george.kyriazis@intel.com>
* swr: [rasterizer codegen] Refactor codegenTim Rowley2017-03-287-158/+215
| | | | | | | | | Move common codegen functions into gen_common.py. v2: change gen_knobs.py to find the template file internally, like the rest of the gen scripts. Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
* st/va: remove assert for single sliceNayan Deshmukh2017-03-281-1/+1
| | | | | | | | | we anyway allow for multiple slices v2: do not remove assert to check for buf->size Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com>
* radeonsi: use DMA for clears with unaligned sizeNicolai Hähnle2017-03-281-19/+27
| | | | | | | | | | Only a small tail needs to be uploaded manually. This is only partly a performance measure (apps are expected to use aligned access). Mostly it is preparation for sparse buffers, which the old code would incorrectly have attempted to map directly. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* radeonsi: CP DMA clear supports unaligned destination addressesNicolai Hähnle2017-03-281-1/+2
| | | | Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* radeonsi: remove the early-out for SDMA in si_clear_bufferNicolai Hähnle2017-03-281-22/+21
| | | | | | | This allows the next patches to be simple while still being able to make use of SDMA even in some unusual cases. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* st/nine: Use atomics for available_texture_memAxel Davy2017-03-261-2/+2
| | | | | | | | | Resource dtor can be executed in the worker thread. Use atomic to avoid threading safety issues. CC: "17.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Axel Davy <axel.davy@ens.fr> Tested-by: James Harvey <lothmordor@gmail.com>
* st/nine: Resolve deadlock in surface/volume dtors when using csmtAxel Davy2017-03-263-5/+17
| | | | | | | | | | | | | | | | | | | | Surfaces and Volumes can be freed in the worker thread. Without this patch, pending_uploads_counter could be non-zero in the Surfaces or Volumes dtor, leading to deadlock. Instead decrease properly the counter before releasing the item. Also avoid another potential deadlock if the item is not properly unlocked: Do not call UnlockRect which will cause deadlock, but free directly using the deadlock safe nine_context_get_pipe_multithread. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99246 CC: "17.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Axel Davy <axel.davy@ens.fr> Tested-by: James Harvey <lothmordor@gmail.com>