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* gallium: implement the backend of threaded GL dispatchMarek Olšák2017-03-164-0/+56
* gallivm: (trivial) remove duplicated lineRoland Scheidegger2017-03-161-1/+0
* draw: (trivial) remove a unnecessary lp_build_alloca()Roland Scheidegger2017-03-161-2/+0
* swr: support layer output in geometry shadersIlia Mirkin2017-03-151-0/+2
* gallium/tgsi: Treat UCMP sources as floats to match the GLSL-to-TGSI pass exp...Francisco Jerez2017-03-152-16/+46
* swr: validate backend state numAttributesTim Rowley2017-03-151-0/+2
* radeonsi: implement TGSI opcodes TEX_LZ and TXF_LZMarek Olšák2017-03-152-6/+16
* gallium: add TGSI opcodes TEX_LZ and TXF_LZMarek Olšák2017-03-154-5/+39
* gallium: add PIPE_CAP_TGSI_TEX_TXF_LZMarek Olšák2017-03-1517-0/+18
* radeonsi: disable sinking common instructions down to the end blockSamuel Pitoiset2017-03-151-0/+11
* tgsi: add missing compute shader entry in tgsi_get_processor_name()Samuel Pitoiset2017-03-151-0/+2
* radeonsi: clean up tex_fetch_ptrs()Samuel Pitoiset2017-03-151-6/+4
* winsys/amdgpu: use drmGetDevice2 APIEmil Velikov2017-03-151-2/+2
* r600: refactor binding code for attach buffer to CB.Dave Airlie2017-03-151-33/+78
* r600: refactor out CB setup.Dave Airlie2017-03-151-104/+143
* r600: refactor texture resource words setup code.Dave Airlie2017-03-151-88/+131
* r600: factor out the code to initialise a buffer resource.Dave Airlie2017-03-151-29/+51
* r600g: make framebuffer atom rely on dual src blend state.Dave Airlie2017-03-154-2/+7
* nir: Rework conversion opcodesJason Ekstrand2017-03-145-22/+22
* gallium/radeon: disable the shader cache if dumping shadersMarek Olšák2017-03-131-0/+5
* radeonsi: mark all bound shader buffer ranges as initializedMarek Olšák2017-03-131-0/+3
* gallium/hud: check NULL return from u_upload_allocJulien Isorce2017-03-131-0/+5
* winsys/radeon: check null return from radeon_cs_create_fence in cs_flushJulien Isorce2017-03-131-11/+13
* winsys/radeon: check null in radeon_cs_create_fenceJulien Isorce2017-03-131-0/+3
* freedreno/ir3: fragz cannot be half precisionRob Clark2017-03-131-0/+6
* freedreno/ir3: optimize less in glslRob Clark2017-03-131-1/+1
* svga: handle P016 format as wellChristian König2017-03-131-0/+1
* st/va: add config support for 10bit decoding v2Christian König2017-03-132-4/+21
* st/va: add support for allocating 10bpp surfacesChristian König2017-03-131-9/+15
* st/va: add support for P010 and P016 formats v3Christian König2017-03-134-3/+22
* st/va: clear the video surface on allocationChristian König2017-03-131-4/+35
* st/va: cleanup error handling in vlVaCreateSurfaces2Christian König2017-03-131-25/+27
* radeon/uvd: enable 10bit HEVC decode v2Christian König2017-03-132-8/+20
* radeon/UVD: fix the decoding target pitch calculationChristian König2017-03-131-1/+1
* vl/video_buffer: add support for P016Christian König2017-03-131-0/+10
* gallium: add P016 formatChristian König2017-03-134-0/+42
* gallium/util: replace pipe_thread_setname() with u_thread_setname()Timothy Arceri2017-03-123-15/+3
* gallium/util: replace pipe_thread_get_time_nano() with u_thread_get_time_nano()Timothy Arceri2017-03-121-17/+1
* gallium/util: replace pipe_thread_create() with u_thread_create()Timothy Arceri2017-03-127-33/+7
* gallium/util: move u_queue.{c,h} to src/utilTimothy Arceri2017-03-123-442/+0
* gallium/util: make use of new u_thread.h in u_queue.{c,h}Timothy Arceri2017-03-122-4/+6
* gallium/util: use standard malloc/calloc/free in u_queue.cTimothy Arceri2017-03-121-10/+10
* gallium/util: move u_string.h to src/util/u_string.hTimothy Arceri2017-03-124-207/+2
* gallium/util: remove unused header from u_string.hTimothy Arceri2017-03-121-1/+0
* gallium/util: remove unused util_strbuf*Timothy Arceri2017-03-121-37/+0
* gallium/util: remove unused util_memmove()Timothy Arceri2017-03-121-20/+0
* st/xa: suffix xa-indent{,.sh} and add a shebang lineEmil Velikov2017-03-102-2/+2
* gallium/tools: use correct shebang for python scriptsEmil Velikov2017-03-106-6/+6
* gallium/tools: do not hardcode bash locationEmil Velikov2017-03-102-2/+2
* gallium/tests: remove execute bit from TGSI shader - vert-uadd.shEmil Velikov2017-03-101-0/+0
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