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* nvc0: fix program dumping, use _debug_printfIlia Mirkin2019-08-071-6/+6
| | | | | | | | | This debug situation is unforunate. debug_printf only does something with DEBUG set, but in practice all that needs to be moved to !NDEBUG. For now, use _debug_printf which always prints. However the whole function is guarded by !NDEBUG. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: add support for ATOMC_WRAP TGSI operationsIlia Mirkin2019-08-072-1/+11
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gallium: redefine ATOMINC_WRAP to be more hardware-friendlyIlia Mirkin2019-08-072-13/+1
| | | | | | | | Both AMD and NVIDIA hardware define it this way. Instead of replicating the logic everywhere, just fix it up in one place. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: limit DPBB context_states_per_bin batches when using gfx9 workaroundPierre-Eric Pelloux-Prayer2019-08-071-1/+5
| | | | | | | | It seems that using 'context_states_per_bin = 1' for DPBB fixes the reported issue. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110214 Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: reduce DPBB persistent_states_per_bin value for APUsPierre-Eric Pelloux-Prayer2019-08-071-1/+2
| | | | | | | | Fixes some reported GPU hangs on RAVEN. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111231 Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix typo in DPBB register fieldPierre-Eric Pelloux-Prayer2019-08-071-1/+4
| | | | | | | Also only set FLUSH_ON_BINNING_TRANSITION for GPU families that needs it (matches what si_emit_dpbb_disable is doing). Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix S_028C48_MAX_ALLOC_COUNT valuePierre-Eric Pelloux-Prayer2019-08-071-1/+1
| | | | | | This field uses "value minus 1" encoding. Reviewed-by: Marek Olšák <[email protected]>
* etnaviv: drop struct etna_3d_stateChristian Gmeiner2019-08-073-17/+1
| | | | | | | Also drop #if 0 code block. Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Philipp Zabel <[email protected]>
* meson,i965: Link with android deps when building for android.Bas Nieuwenhuizen2019-08-071-2/+2
| | | | | | | | | | | The DBG marco in brw_blorp.c ends up calling an android log function: error: undefined reference to '__android_log_print' v2: On suggestion from Lionel, hang the Android dependency onto a new libintel_common dependency. Reviewed-by: Lionel Landwerlin <[email protected]>
* gallium/dump: add missing query-type to short-listErik Faye-Lund2019-08-071-0/+1
| | | | | | Signed-off-by: Erik Faye-Lund <[email protected]> Fixes: 3f6b3d9db72 ("gallium: add PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE") Reviewed-by: Marek Olšák <[email protected]>
* gallium/dump: add missing query-type to short-listErik Faye-Lund2019-08-071-0/+1
| | | | | | | Signed-off-by: Erik Faye-Lund <[email protected]> Fixes: a677799e51a ("gallium: add PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE and corresponding cap") Reviewed-by: Marek Olšák <[email protected]>
* clover: Fix build after clang r367864Jan Vesely2019-08-061-2/+8
| | | | | | | | v2: Drop special case of llvm-9 Signed-off-by: Jan Vesely <[email protected]> Acked-by: Dieter Nützel <[email protected]> Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Aaron Watry <[email protected]>
* mesa: freedreno: Android.registers.mk: Fix up register xml.h file generationJohn Stultz2019-08-072-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | The current Androdi.registers.mk file causes build failures that look like: FAILED: external/mesa3d/src/freedreno/Android.registers.mk:49: error: implicit rules are obsolete: out/target/product/linaro_db845c/gen/STATIC_LIBRARIES/libfreedreno_registers_intermediates/registers/%.xml.h Caused by the following Android build rule change: https://android.googlesource.com/platform/build/+/HEAD/Changes.md#implicit_rules I tried to replace this with something similar to the static pattern suggested in the URL above, but ended up getting all the xml.h files generated using only the first a2xx.xml source file. So I've fallen back to explicitly defining the make rules for each. Additionally, we needed to provide the proper LOCAL_EXPORT_C_INCLUDE_DIRS and add the defined static library to the components that depend on the register headers. Acked-by: Eric Anholt <[email protected]> Signed-off-by: John Stultz <[email protected]>
* mesa: Add ir3/ir3_nir_imul.c generation to Android.mkJohn Stultz2019-08-071-0/+8
| | | | | | | | | | | | | | | | | | | | | | With current master we're seeing build failures with AOSP: error: undefined symbol: ir3_nir_lower_imul This is due to the ir3_nir_imul.c file not being generated in the Android.mk files. This patch simply adds it to the Android build, after which thigns build and book ok on db410c. Cc: Rob Clark <[email protected]> Cc: Emil Velikov <[email protected]> Cc: Amit Pundir <[email protected]> Cc: Sumit Semwal <[email protected]> Cc: Alistair Strachan <[email protected]> Cc: Greg Hartman <[email protected]> Cc: Tapani Pälli <[email protected]> Reviewed-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: John Stultz <[email protected]>
* panfrost: Take into account a index_bias for glDrawElementsBaseVertex callsRohan Garg2019-08-061-9/+9
| | | | | | | | | | | | | | Midgard does not accept a index_bias directly and relies instead on a bias correction offset (offset_bias_correction) in order to calculate the unbiased vertex index. We need to make sure we adjust offset_start and vertex_count in order to take into account the index_bias as required by a glDrawElementsBaseVertex call and then supply a additional offset_bias_correction to the hardware. Signed-off-by: Rohan Garg <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* mesa/gallium: add dric option to allow overriding GL vendor stringTimothy Arceri2019-08-073-0/+9
| | | | | | | Will be used in the following patch. Reviewed-by: Marek Olšák <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93551
* tgsi_to_nir: add a few needed double opcodesMarek Olšák2019-08-061-0/+6
| | | | | | | | | for internal radeonsi shaders v2 (Connor): - Split out prep work from adding opcodes, and rewrite the former Reviewed-by: Marek Olšák <[email protected]>
* tgsi_to_nir: implement a few needed 64-bit integer opcodesMarek Olšák2019-08-061-0/+5
| | | | | | | | | | for internal radeonsi shaders v2 (Connor): - Split this out from the prep work, and rework the former - Add support for U64SNE Reviewed-by: Marek Olšák <[email protected]>
* ttn: Prepare for 64-bit sources and destinationsConnor Abbott2019-08-061-5/+29
| | | | | | v2: Properly handle 32->64 bit conversions Reviewed-by: Marek Olšák <[email protected]>
* ttn: Use 1-bit NIR comparison opcodesConnor Abbott2019-08-061-24/+19
| | | | | | | | | We shouldn't be using the versions that output a 32-bit boolean, since nir_opt_algebraic won't optimize them as well. Drivers will lower these to the 32-bit versions after optimizing, if appropriate. Also, this will make implementing 64-bit comparisons easier. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: enable EXT_shader_image_load_storePierre-Eric Pelloux-Prayer2019-08-061-0/+2
| | | | | | This depends on LLVM 10 because this needs https://reviews.llvm.org/D65283 Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add support for nir atomic_inc_wrap/atomic_dec_wrapPierre-Eric Pelloux-Prayer2019-08-061-0/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add support for tgsi ATOMDEC_WRAP / ATOMINC_WRAP opcodesPierre-Eric Pelloux-Prayer2019-08-061-0/+23
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium: add PIPE_CAP_TGSI_ATOMINC_WRAP to indicate supportPierre-Eric Pelloux-Prayer2019-08-067-0/+7
| | | | Reviewed-by: Marek Olšák <[email protected]>
* tgsi: add ATOMICINC_WRAP/ATOMICDEC_WRAP opcodePierre-Eric Pelloux-Prayer2019-08-065-2/+40
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/gfx10: enable all CUs for GS if NGG is never usedMarek Olšák2019-08-061-2/+4
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: add global use_ngg and use_ngg_streamout flagsMarek Olšák2019-08-069-32/+41
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: remove an obsolete VGT_REUSE_OFF workaroundMarek Olšák2019-08-062-9/+0
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: disable LATE_ALLOC_GS on Navi14Marek Olšák2019-08-061-1/+8
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: implement a bug workaround for GE_PC_ALLOCMarek Olšák2019-08-062-11/+12
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: implement a bug workaround for NGG -> legacy transitionsMarek Olšák2019-08-062-2/+16
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: implement a GE bug workaroundMarek Olšák2019-08-061-0/+18
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: set GE_CNTL for tessellation correctlyMarek Olšák2019-08-061-5/+11
| | | | | | | to match PAL Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: simplify NGG code in si_update_shadersMarek Olšák2019-08-061-9/+3
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: fix input VGPRs for legacy VSMarek Olšák2019-08-062-8/+11
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: make sure that rasterizer state != NULL and remove all NULL checkingMarek Olšák2019-08-067-17/+23
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: make sure that DSA state != NULL and remove all NULL checkingMarek Olšák2019-08-067-12/+19
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: make sure that blend state != NULL and remove all NULL checkingMarek Olšák2019-08-067-55/+52
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: DCC MSAA blending bug - include logic op, limit to Navi14 and olderMarek Olšák2019-08-062-2/+9
| | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: determine accurately whether logic op is enabledMarek Olšák2019-08-061-3/+5
| | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: skip draw calls with 0-sized index buffersMarek Olšák2019-08-061-0/+6
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/nir: lower PS inputs before scanning the shaderMarek Olšák2019-08-063-95/+86
| | | | | | | Lowering PS inputs can eliminate some of them, which messes up persp/linear barycentric coord usage info. Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/nir: handle key.mono.u.ps.interpolate_at_sample_force_centerMarek Olšák2019-08-061-1/+4
| | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: add missing prints into si_dump_shader_keyMarek Olšák2019-08-061-0/+9
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: disable SDMA image copies on dGPUs to fix corruption in gamesMarek Olšák2019-08-061-1/+9
| | | | | Cc: 19.1 19.2 <[email protected]> Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* iris: Handle vertex shader with window space positionDanylo Piliaiev2019-08-063-5/+44
| | | | | | | | | | Iris advertises support for PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION so let's actually implement it. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110657 Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* lima: fix pipe_debug_callback warningsErico Nunes2019-08-063-5/+5
| | | | | Signed-off-by: Erico Nunes <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]>
* lima/ppir: move sin/cos input scaling into NIRVasily Khoruzhick2019-08-065-58/+69
| | | | | Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* iris: Increase BATCH_SZ to 64kBKenneth Graunke2019-08-061-1/+1
| | | | | This seems to improve performance by roughly ~1% across the board. Thanks to Rafael Antognolli and Dan Walsh for their help tuning.
* etnaviv: support 3D and 2D array texturesJonathan Marek2019-08-064-23/+74
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
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