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* r600g,radeonsi: consolidate get_compute_paramMarek Olšák2014-01-287-267/+162
| | | | | | | v2: added fprintf to r600_get_llvm_processor_name Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g,radeonsi: consolidate get_paramf and get_video_paramMarek Olšák2014-01-284-118/+70
| | | | | | | | | | radeonsi now reports PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE = true if UVD support isn't available. It's what all the other drivers do. Also, some #include directives were missing in radeon_uvd.h. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g,radeonsi: consolidate variables for CS tracingMarek Olšák2014-01-2810-46/+42
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g,radeonsi: consolidate get_timestamp, get_driver_query_infoMarek Olšák2014-01-284-41/+34
| | | | | | | This enables more queries for the Gallium HUD with radeonsi. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g,radeonsi: consolidate get_name and get_vendor queriesMarek Olšák2014-01-283-74/+50
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon: place context-related functions first in r600_pipe_common.cMarek Olšák2014-01-281-79/+87
| | | | | | | To follow the unwritten convention of r600g and radeonsi. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g,radeonsi: consolidate the contents of r600_resource.cMarek Olšák2014-01-2813-163/+45
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: advertise the pipeline statistics queryMarek Olšák2014-01-281-1/+1
| | | | | | | | | | Implemented by the common code. You can now visualize the statistics with the HUD, see GALLIUM_HUD=help for all available queries. For example: GALLIUM_HUD=clipper-primitives-generated Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: use queries from r600gMarek Olšák2014-01-289-757/+40
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g: remove a no-op while loopMarek Olšák2014-01-281-1/+1
| | | | | | | | | | | for (;;) { } while (); I was surprised to see such a statement. Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g: convert query emission code to radeon_emitMarek Olšák2014-01-281-50/+50
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g: only emit NOP relocations for queries if VM is disabledMarek Olšák2014-01-283-23/+19
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* r600g: move queries to drivers/radeonMarek Olšák2014-01-2812-239/+282
| | | | | Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* mesa: Change many Type P MESA_FORMATs to meet naming specMark Mueller2014-01-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conversion of Type P formats as follows (w/related comment fixes): s/MESA_FORMAT_RGB565\b/MESA_FORMAT_B5G6R5_UNORM/g s/MESA_FORMAT_RGB565_REV\b/MESA_FORMAT_R5G6B5_UNORM/g s/MESA_FORMAT_ARGB4444\b/MESA_FORMAT_B4G4R4A4_UNORM/g s/MESA_FORMAT_ARGB4444_REV\b/MESA_FORMAT_A4R4G4B4_UNORM/g s/MESA_FORMAT_RGBA5551\b/MESA_FORMAT_A1B5G5R5_UNORM/g s/MESA_FORMAT_XBGR8888_SNORM\b/MESA_FORMAT_R8G8B8X8_SNORM/g s/MESA_FORMAT_XBGR8888_SRGB\b/MESA_FORMAT_R8G8B8X8_SRGB/g s/MESA_FORMAT_ARGB1555\b/MESA_FORMAT_B5G5R5A1_UNORM/g s/MESA_FORMAT_ARGB1555_REV\b/MESA_FORMAT_A1R5G5B5_UNORM/g s/MESA_FORMAT_AL44\b/MESA_FORMAT_L4A4_UNORM/g s/MESA_FORMAT_RGB332\b/MESA_FORMAT_B2G3R3_UNORM/g s/MESA_FORMAT_ARGB2101010\b/MESA_FORMAT_B10G10R10A2_UNORM/g s/MESA_FORMAT_Z24_S8\b/MESA_FORMAT_S8_UINT_Z24_UNORM/g s/MESA_FORMAT_S8_Z24\b/MESA_FORMAT_Z24_UNORM_S8_UINT/g s/MESA_FORMAT_X8_Z24\b/MESA_FORMAT_Z24_UNORM_X8_UINT/g s/MESA_FORMAT_Z24_X8\b/MESA_FORMAT_X8Z24_UNORM/g s/MESA_FORMAT_RGB9_E5_FLOAT\b/MESA_FORMAT_R9G9B9E5_FLOAT/g s/MESA_FORMAT_R11_G11_B10_FLOAT\b/MESA_FORMAT_R11G11B10_FLOAT/g s/MESA_FORMAT_Z32_FLOAT_X24S8\b/MESA_FORMAT_Z32_FLOAT_S8X24_UINT/g s/MESA_FORMAT_ABGR2101010_UINT\b/MESA_FORMAT_R10G10B10A2_UINT/g s/MESA_FORMAT_XRGB4444_UNORM\b/MESA_FORMAT_B4G4R4X4_UNORM/g s/MESA_FORMAT_XRGB1555_UNORM\b/MESA_FORMAT_B5G5R5X1_UNORM/g s/MESA_FORMAT_XRGB2101010_UNORM\b/MESA_FORMAT_B10G10R10X2_UNORM/g s/MESA_FORMAT_AL88\b/MESA_FORMAT_L8A8_UNORM/g s/MESA_FORMAT_AL88_REV\b/MESA_FORMAT_A8L8_UNORM/g s/MESA_FORMAT_AL1616\b/MESA_FORMAT_L16A16_UNORM/g s/MESA_FORMAT_AL1616_REV\b/MESA_FORMAT_A16L16_UNORM/g s/MESA_FORMAT_RG88\b/MESA_FORMAT_G8R8_UNORM/g s/MESA_FORMAT_GR88\b/MESA_FORMAT_R8G8_UNORM/g s/MESA_FORMAT_GR1616\b/MESA_FORMAT_R16G16_UNORM/g s/MESA_FORMAT_RG1616\b/MESA_FORMAT_G16R16_UNORM/g s/MESA_FORMAT_SRGBA8\b/MESA_FORMAT_A8B8G8R8_SRGB/g s/MESA_FORMAT_SARGB8\b/MESA_FORMAT_B8G8R8A8_SRGB/g s/MESA_FORMAT_SLA8\b/MESA_FORMAT_L8A8_SRGB/g Conflicts: src/mesa/drivers/dri/i965/brw_surface_formats.c src/mesa/main/format_pack.c src/mesa/main/format_unpack.c src/mesa/main/formats.c src/mesa/main/texformat.c src/mesa/main/texstore.c
* mesa: Rename 4 color component unsigned byte MESA_FORMATsMark Mueller2014-01-271-2/+2
| | | | | | | | | | | | | Change all 4 color component unsigned byte formats to meet spec for P Type formats: s/MESA_FORMAT_RGBA8888\b/MESA_FORMAT_A8B8G8R8_UNORM/g s/MESA_FORMAT_RGBA8888_REV\b/MESA_FORMAT_R8G8B8A8_UNORM/g s/MESA_FORMAT_ARGB8888\b/MESA_FORMAT_B8G8R8A8_UNORM/g s/MESA_FORMAT_ARGB8888_REV\b/MESA_FORMAT_A8R8G8B8_UNORM/g s/MESA_FORMAT_RGBX8888\b/MESA_FORMAT_X8B8G8R8_UNORM/g s/MESA_FORMAT_RGBX8888_REV\b/MESA_FORMAT_R8G8B8X8_UNORM/g s/MESA_FORMAT_XRGB8888\b/MESA_FORMAT_B8G8R8X8_UNORM/g s/MESA_FORMAT_XRGB8888_REV\b/MESA_FORMAT_X8R8G8B8_UNORM/g
* mesa: change gl_format to mesa_formatMark Mueller2014-01-271-2/+2
| | | | s/\bgl_format\b/mesa_format/g. Use better name for Mesa Formats enum
* r600g/compute: Emit DEALLOC_STATE on cayman after dispatching a compute shader.Tom Stellard2014-01-274-14/+10
| | | | | | | | | | | | This is necessary to prevent the next SURFACE_SYNC packet from hanging the GPU. https://bugs.freedesktop.org/show_bug.cgi?id=73418 Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]> CC: "9.2" "10.0" <[email protected]>
* nv50, nvc0: update reported glsl version to 330Ilia Mirkin2014-01-272-2/+2
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: add more RGB10A2 formatsChristoph Bumiller2014-01-271-0/+7
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* nv50: enable seamless cube maps on all hwIlia Mirkin2014-01-271-1/+1
| | | | | | | | | | Some of the hardware support is missing. The NVIDIA-provided driver, which claims seamless cube map support fails the relevant tests as well. As this is the last extension before we can have OpenGL 3.2, doing this allows us to expose geometry shaders without doing the additional work involved in supporting ARB_geometry_shader4. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: report glsl 1.50 now that gp tests passIlia Mirkin2014-01-271-1/+1
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: add support for texelFetch'ing MS textures, ARB_texture_multisampleIlia Mirkin2014-01-277-7/+164
| | | | | | | | | | | | | | Creates two areas in the AUX constbuf: - Sample offsets for MS textures - Per-texture MS settings When executing a texelFetch with a MS sampler, looks up that texture's settings and adjusts the parameters given to the texfetch instruction. With this change, all the ARB_texture_multisample piglits pass, so turn on PIPE_CAP_TEXTURE_MULTISAMPLE. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: copy nvc0's get_sample_position implementationIlia Mirkin2014-01-271-0/+46
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: add comments about CB_AUX contentsIlia Mirkin2014-01-273-5/+15
| | | | | | | Updates a few inconsistencies as well, like the size of the buffer, location of the runout, etc. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: don't forget to also clear additional layersIlia Mirkin2014-01-271-5/+27
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: don't forget to also clear additional layersIlia Mirkin2014-01-271-5/+27
| | | | | | Fixes most of the tests/spec/gl-3.2/layered-rendering/* piglits. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: allocate an extra code bo to avoid dmesg spamIlia Mirkin2014-01-271-1/+5
| | | | | | | | | Each code BO is a heap that allocates at the end first, and so GPs are allocated at the very end of the allocated space. When executing, we see PAGE_NOT_PRESENT errors for the next page. Just over-allocate to make sure that there's something there. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: GP_REG_ALLOC_RESULT must be positiveIlia Mirkin2014-01-271-0/+2
| | | | | | Set max_out to 1 when there are no outputs. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: VP_RESULT_MAP_SIZE has to be positiveIlia Mirkin2014-01-271-0/+4
| | | | | | | | Make sure that we never try to use a 0-sized map. This can happen when using a gp, so add a dummy mapping when computing vp_gp_mapping in that case. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: enable primitive id generation when it is an FP input without GPIlia Mirkin2014-01-272-9/+8
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: handle gl_Layer writes in GPIlia Mirkin2014-01-274-1/+19
| | | | | | | | Marks gl_Layer as only having one component, and makes sure to keep track of where it is and emit it in the output map, since it is not an input to the FP. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: properly set the PRIMITIVE_ID enable flag when it is a gp input.Ilia Mirkin2014-01-271-0/+3
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: add support for gl_PrimitiveIDInIlia Mirkin2014-01-273-5/+11
| | | | | | | | | | | | | Note that the primitive id is stored in a[0x18], while usually the geometry instructions are of the form a[$a1 + 0x4] which gets mapped to p[] space. We need to avoid the change from a[] to p[] here, so it's keyed on whether the access is indirect or not. Note that there's also a use-case for accessing e.g. a[$r1], however that's not supported for now. (Could be added by checking the register file of the indirect parameter.) Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: fix support for shader input + immediate in gpIlia Mirkin2014-01-272-1/+7
| | | | | | This only works for up to $a3, hopefully we won't go that high. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: disallow shader input + cbuf in same instruction in gpIlia Mirkin2014-01-271-1/+6
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: disallow predicates on emit/restart opsIlia Mirkin2014-01-271-1/+2
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* nv50: allow vert_count to be >255Ilia Mirkin2014-01-271-1/+1
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: add support for geometry shadersBryan Cain2014-01-274-6/+39
| | | | | | | | | | Layer output probably doesn't work yet, but other than that everything seems to be working. Signed-off-by: Bryan Cain <[email protected]> [calim: fix up minor bugs, code formatting] Signed-off-by: Christoph Bumiller <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: delay calculation of indirect addressesBryan Cain2014-01-273-13/+136
| | | | | | | | | | | | | | Instead of emitting an SHL 4 io an address register on the TGSI ARL and UARL instructions, emit the shift when the loaded address is actually used. This is necessary because input vertex and attribute indices in geometry shaders on nv50 need to be shifted left by 2 instead of 4. Signed-off-by: Bryan Cain <[email protected]> [calim: various updates to the indirect address logic] Signed-off-by: Christoph Bumiller <[email protected]> [imirkin: remove OP_MAD change that calim made, add OP_RESTART handling same as OP_EMIT for code flow analysis] Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: fix PFETCH and add RDSV to get VSTRIDE for GPsChristoph Bumiller2014-01-273-5/+59
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* nv50/ir: txg not available on nvaa/nvacIlia Mirkin2014-01-271-1/+1
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50, nvc0: only clear out the buffers that we were asked to clearIlia Mirkin2014-01-272-14/+24
| | | | | | | Fixes fbo-drawbuffers-none glClearBuffer piglit test. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* nv50, nvc0: clear out RT on a null cbufIlia Mirkin2014-01-274-8/+52
| | | | | | | | | | | | This is needed since commit 9baa45f78b (st/mesa: bind NULL colorbuffers as specified by glDrawBuffers). This implementation is highly based on a larger commit by Christoph Bumiller <[email protected]> in his gallium-nine branch. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* nv50: don't leak heap on tls alloc failureIlia Mirkin2014-01-271-1/+3
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nouveau/codegen: set dType to S32 for OP_NEG U32Ilia Mirkin2014-01-273-7/+27
| | | | | | | | | | | | | | | | | | | | | | It doesn't make sense to do an OP_NEG from U32 to U32. This was manifested on nv50 in glsl-fs-atan-3 which was generating a UMAD TEMP[0].x, TEMP[0].xxxx, -TEMP[5].xxxx, TEMP[0].xxxx instruction. (For some reason, nvc0 causes a different shader to be generated.) This led to a cvt neg u32 $r1 u32 $r1 Which did not yield the desired result. This changes the final output to cvt neg s32 $r1 u32 $r1 which produces the desired output and the piglit tests passes. My assumption is that this is also what we want on nvc0, but could not test as there was no suitable shader that generated the problem instruction. Signed-off-by: Ilia Mirkin <[email protected]>
* util/u_vbuf: correct map offset calculation for crazy offsetsIlia Mirkin2014-01-271-1/+1
| | | | | | | | | When the min_index is very large (or very negative), the multipliation can overflow 32 bits and result in an incorrect map pointer modification. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* translate: deal with size overflows by casting to ptrdiff_tIlia Mirkin2014-01-272-3/+7
| | | | | | | | | | | This was discovered as a result of the draw-elements-base-vertex-neg piglit test, which passes very negative offsets in, followed up by large indices. The nouveau code correctly adjusts the pointer, but the translate code needs to do the proper inverse correction. Similarly fix up the SSE code to do a 64-bit multiply to compute the proper offset. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium/rtasm: handle mmap failures appropriatelyEmil Velikov2014-01-271-3/+7
| | | | | | | | | | | | | | For a variety of reasons mmap (selinux and pax to name a few) and can fail and with current code. This will result in a crash in the driver, if not worse. This has been the case since the inception of the gallium copy of rtasm. Cc: 9.1 9.2 10.0 <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73473 Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]>
* svga: rename "tex_usage" to "bindings", add commentsBrian Paul2014-01-241-7/+11
| | | | Trivial.
* svga: fix PS output register setup regressionBrian Paul2014-01-232-3/+5
| | | | | | | | | | | | Fixes glean fragProg1 regression caused by commit b9f68d927ea (implement TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS). This bug only appears when the fragment shader emits fragment.Z before color outputs. The bug was caused by confusion between register indexes and semantic indexes. Also added some comments to better explain register indexing. Reviewed-by: Jose Fonseca <[email protected]>
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