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* radeonsi/uvd: don't call ws->query_infoMarek Olšák2017-11-291-9/+6
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move video queries into si_get.cMarek Olšák2017-11-294-168/+151
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove more functions from r600_pipe_common.cMarek Olšák2017-11-293-35/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move/remove ac_shader_binary helpersMarek Olšák2017-11-294-27/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move all get functions to si_get.c; disk_cache_create to si_pipe.cMarek Olšák2017-11-296-852/+903
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove R600_CONTEXT_* flagsMarek Olšák2017-11-297-31/+27
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: just include si_pipe.h in r600_query.cMarek Olšák2017-11-293-7/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove some definitions and helpers from r600_pipe_common.hMarek Olšák2017-11-2913-136/+125
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't use fast color clear for small surfacesMarek Olšák2017-11-291-0/+17
| | | | | | This removes 35+ clear eliminate passes from DOTA 2. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: unify code setting dirty_level_mask for fast clearMarek Olšák2017-11-291-14/+11
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clean up si_do_fast_color_clear parametersMarek Olšák2017-11-291-10/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove r600_common_context::clear_bufferMarek Olšák2017-11-295-20/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move r600_test_dma.c into si_test_dma.cMarek Olšák2017-11-298-20/+20
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move si_pipe_clear_buffer into si_cp_dma.cMarek Olšák2017-11-292-61/+61
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move all clear() code into si_clear.cMarek Olšák2017-11-299-719/+764
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: enable DCC with MSAA for VIMarek Olšák2017-11-295-2/+15
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: implement fast color clear for DCC with MSAA for VIMarek Olšák2017-11-291-5/+30
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add a workaround for blending with DCC and MSAAMarek Olšák2017-11-291-8/+23
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clear PIPE_IMAGE_ACCESS_WRITE when it's invalid to be on the safe sideMarek Olšák2017-11-291-0/+10
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/surface: enable DCC computation for MSAAMarek Olšák2017-11-291-1/+2
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix layered DCC fast clearMarek Olšák2017-11-291-1/+4
| | | | | Cc: 17.2 17.3 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* r600: lds load cleanups.Dave Airlie2017-11-291-6/+8
| | | | | | This is just some cleanups on top of the last patch from my compute branch. Signed-off-by: Dave Airlie <[email protected]>
* r600_shader: only load from LDS what is really usedGert Wollny2017-11-291-7/+26
| | | | | | | | Use the destination write mask to determine which values are really to be read from LDS and load only these. Reviewed-by: Dave Airlie <[email protected]> Signed-off-by: Gert Wollny <[email protected]>
* r600/sb: handle jump after target to end of program. (v2)Dave Airlie2017-11-291-0/+5
| | | | | | | | | | | | | | | | This fixes hangs on cayman with tests/spec/arb_tessellation_shader/execution/trivial-tess-gs_no-gs-inputs.shader_test This has a single if/else in it, and when this peephole activated, it would set the jump target to NULL if there was no instruction after the final POP. This adds a NOP if we get a jump in this case, and seems to fix the hangs, so we have a valid target for the ELSE instruction to go to, instead of 0 (which causes infinite loops). v2: update last_cf correctly. (I had some other patches hide this) Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* meson: build virgl driverDylan Baker2017-11-285-1/+103
| | | | | | | Build tested only. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: build svga driver on linuxDylan Baker2017-11-284-1/+142
| | | | | | | Build tested only. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: build r600 driverDylan Baker2017-11-283-3/+138
| | | | | | | | | v4: - Ensure inc_amd_common defined when radeonsi is disabled (needed by r600) Signed-off-by: Dylan Baker <[email protected]> Tested-by: Aaron Watry <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: build r300 driverDylan Baker2017-11-283-5/+172
| | | | | | | This is build tested only Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: build i915g driverDylan Baker2017-11-284-3/+110
| | | | | | | Build tested only. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* svga: move svga_is_format_supported() to svga_format.cBrian Paul2017-11-283-121/+129
| | | | | | where the other format-related functions live. Reviewed-by: Charmaine Lee <[email protected]>
* svga: s/unsigned/SVGA3dDevCapIndex/Brian Paul2017-11-281-3/+6
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* vc4: check preprocessor token existence using #ifdef instead of #ifEric Engestrom2017-11-281-3/+3
| | | | | | | (other uses of USE_VC4_SIMULATOR are already correct) Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* st/dri: replace hard-coded array size with ARRAY_SIZE()Eric Engestrom2017-11-281-1/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/gfx9: simplify condition for on-chip ESGSNicolai Hähnle2017-11-281-3/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: clarify that si_shader_selector::esgs_itemsize is set for the ES partNicolai Hähnle2017-11-281-1/+3
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: use si_shader_context instead of lp_build_context in more placesNicolai Hähnle2017-11-281-27/+23
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: cleanup si_initialize_color_surfaceNicolai Hähnle2017-11-281-12/+12
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: avoid attempting to create CMASK if the tiling mode doesn't have itNicolai Hähnle2017-11-281-0/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: check that we don't leak fine.buf referencesNicolai Hähnle2017-11-281-0/+2
| | | | | | Just as an added precaution. Reviewed-by: Marek Olšák <[email protected]>
* amd/common: sid.h cleanupsNicolai Hähnle2017-11-281-1/+1
| | | | | | | Fix a bunch of labels indicating when registers were added/removed and normalize the SI-class GRBM_GFX_INDEX. Reviewed-by: Marek Olšák <[email protected]>
* ac: change legacy_surf_level::slice_size to dword unitsMarek Olšák2017-11-279-30/+32
| | | | | | | | | The next commit will reduce the size even more. v2: typecast to uint64_t manually v3: add more typecasts, add asserts Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: pack ac_surface betterMarek Olšák2017-11-272-7/+7
| | | | | | r600_texture: 1736 -> 1488 bytes Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: always initialize max_forced_staging_uploadsMarek Olšák2017-11-271-0/+2
| | | | | | | | | r600_resource is malloc'd. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103808 Fixes: 4b0dc098b256 ("gallium/u_threaded: don't map big VRAM buffers for the first upload directly") Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove an old hack for evergreenMarek Olšák2017-11-271-10/+0
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: set COMPUTE_RESOURCE_LIMITS.FORCE_SIMD_DIST when profitableMarek Olšák2017-11-271-1/+16
| | | | | | ported from Vulkan Reviewed-by: Nicolai Hähnle <[email protected]>
* r600/eg: dump event type in dumpsDave Airlie2017-11-271-0/+1
| | | | | | This just makes it easier to debug some things. Signed-off-by: Dave Airlie <[email protected]>
* nouveau/compiler: Allow to omit line numbers when printing instructionsTobias Klausmann2017-11-265-4/+13
| | | | | | | | | | | | | | | | This comes in handy when checking "NV50_PROG_DEBUG=1" outputs with diff! V2: - Use environmental variable (Karol Herbst) V3: - Use the already populated nv50_ir_prog_info to forward information to the print pass (Pierre Moreau) V4: - get rid of default value in PrintPass constructor Signed-off-by: Tobias Klausmann <[email protected]> Reviewed-by: Pierre Moreau <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* radeonsi: try flushing unflushed fences in si_fence_finish even when timeout ↵Nicolai Hähnle2017-11-261-3/+3
| | | | | | | | | | | | | | | | | == 0 Under certain conditions, waiting on a GL sync objects should act like a flush, regardless of the timeout. Portal 2, CS:GO, and presumably other Source engine games rely on this behavior and hang during loading without this fix. Fixes: bc65dcab3bc4 ("radeonsi: avoid syncing the driver thread in si_fence_finish") Signed-off-by: Marek Olšák <[email protected]> Tested-by: Kai Wasserbäch <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103902 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103904
* nv50/ir: move LateAlgebraicOpt to the very endIlia Mirkin2017-11-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | Memory loads can take offsets, but the SHLADD will often attempt to consume the offsets too. As there may be multiple memory loads with the same base but different offsets, those would end up in a SHLADD instead of the offset of the memory operation. This moves the pass after we've had a chance to attempt to propagate immediate adds into the indirect offset. total instructions in shared programs : 6580681 -> 6567716 (-0.20%) total gprs used in shared programs : 944261 -> 943375 (-0.09%) total shared used in shared programs : 0 -> 0 (0.00%) total local used in shared programs : 15328 -> 15328 (0.00%) total bytes used in shared programs : 60339896 -> 60221504 (-0.20%) local shared gpr inst bytes helped 0 0 555 2698 2698 hurt 0 0 138 336 336 Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: when merging immediates/consts, load directlyIlia Mirkin2017-11-261-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | When a MERGE operation gets its constraint moves added, it susbstantially extends live ranges to be reusing an immediate from earlier in the program (not to mention the silliness of loading an immediate into a register, and then moving into another register). We detect these scenarios and insert moves that take the immediate or constbuf load directly into the register. If it's the last use, then we can just move that operation to the closer location. With SM35 (255 regs) we get these results: total instructions in shared programs : 6583670 -> 6580681 (-0.05%) total gprs used in shared programs : 950818 -> 944261 (-0.69%) total shared used in shared programs : 0 -> 0 (0.00%) total local used in shared programs : 15328 -> 15328 (0.00%) total bytes used in shared programs : 60367456 -> 60339896 (-0.05%) local shared gpr inst bytes helped 0 0 4584 3186 3186 hurt 0 0 55 968 968 I suspect they will be better for SM20 and SM30. Signed-off-by: Ilia Mirkin <[email protected]>
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