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* radeonsi/gfx9: don't flush TC L2 between rendering and texturing if not neededMarek Olšák2017-08-223-34/+47
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: use correct TC flush flags when invalidating CB & DBMarek Olšák2017-08-221-7/+21
| | | | | | Now we can finally stop flushing L2 data. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: don't use GS scenario A for VS writing ViewportIndexMarek Olšák2017-08-221-7/+3
| | | | | | Vulkan doesn't do it anymore. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: clean up EOP_DATA_SEL magic numbersMarek Olšák2017-08-223-6/+12
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: set 'not a query' for r600_gfx_write_event_eop correctlyMarek Olšák2017-08-223-3/+5
| | | | | | 0 is PIPE_QUERY_OCCLUSION_COUNTER, which is not what we want. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: prevent shader-db crashesMarek Olšák2017-08-221-1/+11
| | | | | | | - don't precompile LS and ES (they don't exist on GFX9), compile as VS instead - don't precompile HS and GS (we don't have LS and ES parts) Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: properly handle imported textures with unexpected swizzle modeMarek Olšák2017-08-221-6/+3
| | | | | Cc: 17.2 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove Constant Engine supportMarek Olšák2017-08-2216-618/+38
| | | | | | | | We have come to the conclusion that it doesn't improve performance. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: add a temporary workaround for a tessellation driver bugMarek Olšák2017-08-221-1/+5
| | | | | | | | | The workaround will do for now. The root cause is still unknown. This fixes new piglit: 16in-1out Cc: 17.1 17.2 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: try to re-use previously deleted bindless descriptor slotsSamuel Pitoiset2017-08-222-7/+31
| | | | | | | | Currently, when the array is full it is resized but it can grow over and over because we don't try to re-use descriptor slots. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: use slot indexes for bindless handlesSamuel Pitoiset2017-08-224-229/+187
| | | | | | | | | | | | | | | Using VRAM address as bindless handles is not a good idea because we have to use LLVMIntToPTr and the LLVM CSE pass can't optimize because it has no information about the pointer. Instead, use slots indexes like the existing descriptors. Note that we use fixed 16-dword slots for both samplers and images. This doesn't really matter because no real apps use image handles. This improves performance with DOW3 by +7%. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add si_emit_global_shader_pointers() helperSamuel Pitoiset2017-08-221-26/+31
| | | | | | | To share common code between rw buffers and bindless descriptors. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: only initialize dirty_mask when CE is usedSamuel Pitoiset2017-08-221-3/+4
| | | | | | | | | Looks like it's useless to initialize that field when CE is unused. This will also allow to declare more than 64 elements for the array of bindless descriptors. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: make some si_descriptors fields 32-bitSamuel Pitoiset2017-08-221-5/+5
| | | | | | | | The number of bindless descriptors is dynamic and we definitely have to support more than 256 slots. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: declare new user SGPR indices for bindless samplers/imagesSamuel Pitoiset2017-08-223-1/+23
| | | | | | | | | A new pair of user SGPR is needed for loading the bindless descriptors from shaders. Because the descriptors are global for all stages, there is no need to add separate indices for GFX9. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/util: add new module that allocate "numbers"Samuel Pitoiset2017-08-223-0/+160
| | | | | | | | Will be used for allocating bindless descriptor slots for RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/gfx9: add performance countersNicolai Hähnle2017-08-221-1/+28
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: extract common code of si_upload_{graphics,compute}_shader_descriptorsNicolai Hähnle2017-08-221-19/+8
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium: remove unused PIPE_DUMP_* definesNicolai Hähnle2017-08-223-25/+7
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ddebug: remove dd_draw_record::driver_state_logNicolai Hähnle2017-08-222-58/+0
| | | | | | It is no longer used. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: emit string markers to log contextNicolai Hähnle2017-08-221-0/+3
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: log decompress blitsNicolai Hähnle2017-08-221-0/+13
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: log draw and compute state into log contextNicolai Hähnle2017-08-224-32/+51
| | | | | | Also add missing trace emits and CS logging for compute launches. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: print saved CS to the log contextNicolai Hähnle2017-08-225-88/+263
| | | | | | | | | | | | Use the auto logger facility, so that CS chunks will be interleaved with other log info. v2: - fix some crashes when not using CE - fix skipping "previous" chunks of current (unflushed) IB - fix error handling in si_begin_cs_debug Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: start using u_log_context for debuggingNicolai Hähnle2017-08-223-83/+199
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: re-order debug state dumpingNicolai Hähnle2017-08-221-7/+8
| | | | | | Keep together the parts that won't use the deferred logging mechanism. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: make si_shader_selector_reference globally visibleNicolai Hähnle2017-08-222-15/+16
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add reference count to si_computeNicolai Hähnle2017-08-222-10/+28
| | | | | | To allow keep-alive for deferred logging. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: implement pipe_context::set_log_contextNicolai Hähnle2017-08-222-0/+12
| | | | | | | | We'll add radeonsi-specific code to set_log_context in later patches, but we may want to log from common code. Hence keep the log pointer in r600_common_context. Reviewed-by: Marek Olšák <[email protected]>
* ddebug: add driver log to record dumpsNicolai Hähnle2017-08-223-0/+30
| | | | Reviewed-by: Marek Olšák <[email protected]>
* gallium: add pipe_context::set_log_contextNicolai Hähnle2017-08-221-0/+14
| | | | Reviewed-by: Marek Olšák <[email protected]>
* util/log: add auto logger facilityNicolai Hähnle2017-08-222-2/+75
| | | | Reviewed-by: Marek Olšák <[email protected]>
* util: add chunk logging moduleNicolai Hähnle2017-08-223-0/+263
| | | | Reviewed-by: Marek Olšák <[email protected]>
* clover/device: Calculate CL_DEVICE_MEM_BASE_ADDR_ALIGN in deviceAaron Watry2017-08-213-1/+9
| | | | | | | | | | | | | | | | | | | | | | The CL CTS queries CL_DEVICE_MEM_BASE_ADDR_ALIGN for a device and then allocates user pointers aligned to that value for its tests. The minimum value is defined as: the size (in bits) of the largest OpenCL built-in data type supported by the device (long16 in FULL profile, long16 or int16 in EMBEDDED profile) for devices that are not of type CL_DEVICE_TYPE_CUSTOM. At the moment, all known devices that support user pointers require CPU page alignment for buffers created from user pointers, so just query that from sysconf. v3: Use std::max instead of MAX2 (Francisco) Add missing unistd include v2: Use system page size instead of a new pipe cap Signed-off-by: Aaron Watry <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by (v2): Jan Vesely <[email protected]>
* svga: replace gotos with conditionals in array drawing codeBrian Paul2017-08-212-32/+32
| | | | | | No Piglit regressions. Reviewed-by: Charmaine Lee <[email protected]>
* llvmpipe: add some whitespace between functions in lp_texture.cBrian Paul2017-08-211-0/+3
| | | | Trivial.
* svga: whitespace clean-up in svga_draw_private.hBrian Paul2017-08-211-29/+27
| | | | Trivial.
* gallium/docs: remove old llvmpipe TODOTimothy Arceri2017-08-221-14/+0
| | | | | | | Features are already covered by features.txt like all the other drivers. Reviewed-by: Eric Engestrom <[email protected]>
* radeonsi: don't prefetch VBO descriptors if vertex elements == NULLMarek Olšák2017-08-212-1/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: don't set up and don't call the fetch shader if there are no VS inputsMarek Olšák2017-08-213-1/+7
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* Android: Fix LLVM duplicated symbols linking for N and MRob Herring2017-08-212-2/+2
| | | | | | | | | | | | | | | | | | | | | Both statically linking libLLVMCore and dynamically linking libLLVM causes duplicated symbols in gallium_dri.so and it fails to dlopen. We don't really need to link libLLVMCore, but just need generated headers to be built first. Dynamically linking to libLLVM instead is enough to do that. Thanks to Qiang Yu for finding the root cause. With this change, we can align all versions and just have libLLVM as a shared lib dependency. This also requires changes in the M and N versions of LLVM to export the include paths for libLLVM. AOSP master is okay. Fixes: 26aee6f4d5a ("Android: rework LLVM build support") Reported-by: Mauro Rossi <[email protected]> Cc: 17.2 <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Qiang Yu <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* st/va: add MJPEG for configLeo Liu2017-08-212-1/+5
| | | | | | | To enable MJPEG HW decode Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: reallocate surface with YUYV streamLeo Liu2017-08-211-0/+17
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: detect MJPEG format from bitstreamLeo Liu2017-08-213-0/+10
| | | | | | | | | To find if the format is supported YUYV by sampling factor which is embedded from bitstream. So we could use this info for buffer reallocation on the correct format. Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/uvd: add YUYV format support for target bufferLeo Liu2017-08-212-3/+5
| | | | | | | Make chroma plane optional for YUYV support Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: reallocate surface when interlacedLeo Liu2017-08-211-0/+22
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/video: MJPEG not support stacked video buffersLeo Liu2017-08-211-1/+5
| | | | | | | So we have to detect it for reallocation of de-interlaced buffers Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: make surface allocate functions more usefullyLeo Liu2017-08-212-4/+5
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/uvd: reconstruct MJPEG bitstreamLeo Liu2017-08-211-0/+136
| | | | | | | | | The current tier 1 mjpeg firmware only supports at the bitstream level, the later tier 2 support will be at the buffers level with newer hardware. Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* st/va: add slice parameter handling for MJPEGLeo Liu2017-08-211-1/+23
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
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