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* freedreno/a3xx: disable filtering for texture buffers and int texturesIlia Mirkin2016-09-111-0/+2
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* st/clover: Define __OPENCL_VERSION__ on the device sideNiels Ole Salscheider2016-09-101-0/+3
| | | | | | | | This is required by the OpenCL standard. Signed-off-by: Niels Ole Salscheider <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Vedran Miletić <[email protected]>
* gm107/ir: allow indirect inputs to be loaded by frag shaderIlia Mirkin2016-09-102-5/+21
| | | | | | | | | Looks like the GM107 IPA op does not allow a separate offset when using an indirect register. Instead we must use AL2P like we do for indirect vertex operations on Kepler+. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* gm107/ir: AL2P writes to a predicate registerIlia Mirkin2016-09-101-0/+1
| | | | | | | | | | | We have to force it to write to predicate 7 (aka PT) in order for it not to mess up another predicate. Unclear what would be returned in the predicate, perhaps an error code for out-of-bounds requests. Blob doesn't seem to check it. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Cc: [email protected]
* radeonsi: flush TC L2 before using a compute indirect bufferMarek Olšák2016-09-091-2/+10
| | | | | | | There is no known test for this. Cc: 12.0 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix the VGT performance tweak for small instancesMarek Olšák2016-09-091-5/+6
| | | | | | | | Based on the VGT spec. The Vulkan driver doesn't do it optimally and they plan to fix it. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove the cache_flush atomMarek Olšák2016-09-097-12/+9
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: replace OUT_CS with radeon_emitMarek Olšák2016-09-091-14/+12
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/radeon: replace OUT_CS with radeon_emitMarek Olšák2016-09-091-7/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* r300g: Set R300_VAP_CNTL on RSxxx to avoid triangle flickeringMax Staudt2016-09-091-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the RSxxx chip series, HW TCL is missing and r300_emit_vs_state() is never called. However, if R300_VAP_CNTL is never set, the hardware (at least the RS690 I tested this on) comes up with rendering artifacts, and parts that are uploaded before this "fix" remain broken in VRAM. This causes artifacts as in fdo#69076 ("triangle flickering"). It seems like this setup needs to happen at least once after power on for 3D rendering to work properly. In the DDX with EXA, this happens in RADEON_SWITCH_TO_3D() when processing an XRENDER Composite or an Xv request. So playing back a video or starting a GTK+2 application fixes 3D rendering for the rest of the session. However, this auto-fix doesn't happen when EXA is not used, such as with GLAMOR or Wayland. This patch ensures the register is configured even in absence of the DDX's EXA module. The register setting is taken from: xf86-video-ati -- RADEONInit3DEngineInternal() mesa/src/mesa/drivers/dri/r300 -- r300EmitClearState() Tested on RS690. CC: <[email protected]> Signed-off-by: Max Staudt <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallium: remove PIPE_BIND_TRANSFER_READ/WRITEMarek Olšák2016-09-0827-88/+18
| | | | | | | | not used in any useful way Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi: unify si_set_optimal_micro_tile_mode call sitesMarek Olšák2016-09-081-8/+4
| | | | | | | There is nothing special happening in those code blocks. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix texture reinterpretation after DCC fast clearMarek Olšák2016-09-081-12/+20
| | | | | | | | | | The problem is that TC-compatible DCC clear codes translate into different clear values when you change the format. I have a new piglit reproducing the issue. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: enable DCC fast clear for 128-bit formatsMarek Olšák2016-09-081-13/+32
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clamp integer clear color values for DCC fast clearMarek Olšák2016-09-081-4/+12
| | | | | | | It should be possible to get TC-compatible fast clear more often now. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* Revert "radeonsi: enable SDMA on CIK"Marek Olšák2016-09-081-0/+4
| | | | | | | This reverts commit 0241d8300f66ee2c6c2c55fe64ac88d76440c591. It doesn't work with mobile Bonaire. It looks like the programming of tiling parameters is wrong on some chips.
* swr: fixes for format mapping and texture sizingTim Rowley2016-09-081-2/+16
| | | | Signed-off-by: Tim Rowley <[email protected]>
* gbm: wire up fence extensionRob Clark2016-09-071-0/+1
| | | | | | | | v2: make fence extension optional to not break non-i965 classic drivers, and move __DRI2_FENCE into core extensions, based on comments from Emil Signed-off-by: Rob Clark <[email protected]>
* freedreno: reject imports with bogus pitchRob Clark2016-09-073-8/+7
| | | | Signed-off-by: Rob Clark <[email protected]>
* radeonsi: skip redundant INDEX_TYPE writesMarek Olšák2016-09-073-20/+32
| | | | | | Ported from Vulkan. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add more unlikely() uses into si_draw_vboMarek Olšák2016-09-071-5/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: skip draws with instance_count == 0Marek Olšák2016-09-071-3/+13
| | | | | | loosely ported from Vulkan Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon/winsyses: fix counting mapped memoryMarek Olšák2016-09-072-0/+16
| | | | | | Not all buffers are unmapped explicitly. Reviewed-by: Nicolai Hähnle <[email protected]>
* st/omx/dec: enable hevc omx decode supportLeo Liu2016-09-062-1/+25
| | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* st/omx/dec/h265: get the reference list for uvdLeo Liu2016-09-061-0/+39
| | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* st/omx/dec/h265: add short term reference picture setsLeo Liu2016-09-061-4/+110
| | | | | | | Specified by subclause 7.3.7 Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* st/omx/dec/h265: add slice headerLeo Liu2016-09-062-2/+216
| | | | | | | Specified by subclause 7.3.6.1 Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* st/omx/dec/h265: add picture parameter setsLeo Liu2016-09-061-0/+98
| | | | | | | Specified by subclause 7.3.2.3 Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* st/omx/dec/h265: add sequence parameter setsLeo Liu2016-09-062-0/+297
| | | | | | | Specified by subclause 7.3.2.2 Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* st/omx/dec: add initial omx hevc supportLeo Liu2016-09-063-0/+160
| | | | | | | Mainly based on the h264 implementation. Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* st/omx/dec: set dst rect to match src sizeLeo Liu2016-09-061-2/+11
| | | | | | | | | | | | | | | When creating interlaced video buffer, hegith set to "template.height = align(tmpl->height/ array_size, VL_MACROBLOCK_HEIGHT);", and we use "template.height *= array_size;" for the buffer height, so it actually aligned with 32. With progressive video buffer it still aligned with 16, thus causing different height between interlaced buffer and progressive buffer for 4K (height=2160), and 720p (height=720). When transcode the video, this will cause the 16 lines corruption at the bottom of the encode video. Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* gallium: switch drivers to the slab allocator in src/utilMarek Olšák2016-09-0630-353/+82
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* amd/addrlib: move addrlib from amdgpu winsys to common codeDave Airlie2016-09-0623-21944/+3
| | | | | Acked-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/util: move endian detect into a separate fileDave Airlie2016-09-061-38/+2
| | | | | | | | This just ports the simpler endian detection bits, addrlib sharing wants this outside gallium. Acked-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeon: move radeon_family/chip_class defintions to commonDave Airlie2016-09-061-84/+2
| | | | | | | This just moves these to a common header file. Acked-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move sid.h/r600d_common.h to a common place.Dave Airlie2016-09-069-9318/+10
| | | | | | | | | | Step one to merging radv would be to move some files around. This only adds the include path to r600/radeonsi, because later we want to avoid having to add it to the generic target paths. Acked-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: remove VPORT_ZMIN/ZMAX from init config statesMarek Olšák2016-09-053-25/+1
| | | | | | | It's part of the viewport state now. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: set VPORT_ZMIN/MAX registers correctlyMarek Olšák2016-09-0512-13/+82
| | | | | | | | | | | | Calculate depth ranges from viewport states and pipe_rasterizer_state::clip_halfz. The evergreend.h change is required to silence a warning. This fixes this recently updated piglit: arb_depth_clamp/depth-clamp-range Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: unify viewport emission codeMarek Olšák2016-09-051-14/+16
| | | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: also do VS_PARTIAL_FLUSH before updating VGT ring pointersMarek Olšák2016-09-051-0/+6
| | | | | | | ported from Vulkan Acked-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix variable naming in si_emit_cache_flushMarek Olšák2016-09-051-31/+31
| | | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't emit CS_PARTIAL_FLUSH if compute is not usedMarek Olšák2016-09-053-1/+5
| | | | | | | for less noise in the HUD Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add HUD queries for counting VS/PS/CS partial flushesMarek Olšák2016-09-054-0/+35
| | | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: rename the num-cs-flushes query to num-ctx-flushesMarek Olšák2016-09-052-5/+5
| | | | | | | num-cs-flushes will mean compute shader flushes Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix a badly implemented GS bug workaroundMarek Olšák2016-09-051-8/+13
| | | | | | | Limit it to geometry shaders and Hawaii. Acked-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix texture format reinterpretation with DCCMarek Olšák2016-09-055-1/+116
| | | | | | | | | | | | DCC is limited in how texture formats can be reinterpreted using texture views. If we get a view format that is incompatible with the initial texture format with respect to DCC, disable DCC. There is a new piglit which tests all format combinations. What works and what doesn't was deduced by looking at the piglit failures. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix Gather4 with integer formatsMarek Olšák2016-09-051-3/+96
| | | | | | | | | | The closed compiler does the same thing. This fixes: GL45-CTS.texture_gather.*-int-* (18 tests) Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix a crash in imageSize for cubemap arraysMarek Olšák2016-09-051-3/+1
| | | | | | | | | | | Sometimes it was f32, other times it was i32. Now it's always i32. This fixes: GL45-CTS.texture_cube_map_array.image_texture_size.texture_size_compute_sh Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix gl_PatchVerticesIn for tessellation evaluation shaderMarek Olšák2016-09-051-1/+6
| | | | | | | | | This fixes: GL45-CTS.tessellation_shader.tessellation_control_to_tessellation_evaluation .gl_PatchVerticesIn Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix cubemaps viewed as 2DMarek Olšák2016-09-051-0/+4
| | | | | | | | | | | This fixes: GL43-CTS.texture_view.view_sampling v2: fix a typo, merge both if statements Cc: [email protected] Reviewed-by: Dave Airlie <[email protected]> (v1) Reviewed-by: Bas Nieuwenhuizen <[email protected]> (v1) Reviewed-by: Nicolai Hähnle <[email protected]>
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