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* r600g: Compute support for CaymanTom Stellard2012-06-065-66/+95
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* xorg: port to new compat API.Dave Airlie2012-06-068-63/+162
| | | | Signed-off-by: Dave Airlie <[email protected]>
* translate_test: add support for half floatsBrian Paul2012-06-061-0/+8
| | | | | | Fixes assertion reported in https://bugs.freedesktop.org/show_bug.cgi?id=44519 but there's still failing cases.
* radeon/llvm: Remove obselete hooks for the ConvertToISA passTom Stellard2012-06-066-87/+1
| | | | | | We can't remove this pass yet, because we need it to convert AMDIL registers in BRANCH* instructions, but we don't need it for instruction conversion any more.
* radeon/llvm: Remove AMDIL MOVE* instructionsTom Stellard2012-06-065-20/+2
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* radeon/llvm: Add isMov() to AMDILInstrInfoTom Stellard2012-06-066-11/+34
| | | | | This enables the CFGStructurizer to work without the AMDIL::MOV* instructions.
* radeon/llvm: Remove deadcode from the AMDILISelLowering classTom Stellard2012-06-062-203/+0
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* radeon/llvm: Don't lower RETURN to S_ENDPGM on SITom Stellard2012-06-062-1/+4
| | | | | Instead create an S_ENDPGM instruction in the CodeEmitter and emit it after all the other instructions.
* radeon/llvm: Remove AMDIL VCREATE* instructionsTom Stellard2012-06-068-97/+12
| | | | This obsoletes the AMDGPULowerInstruction pass.
* radeon/llvm: Remove AMDIL LOADCONST* instructionsTom Stellard2012-06-0613-322/+33
| | | | This obsoletes the R600LowerInstruction and SIPropagateImmReads passes.
* nouveau: fix scratch buffer leakMarcin Slusarz2012-06-054-3/+15
| | | | ...and create common function for destroying nouveau_context
* nv50: fix nv50_stream_output_state leakMarcin Slusarz2012-06-051-0/+3
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* nv50: fix symbol table memory leakMarcin Slusarz2012-06-051-0/+3
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* radeon/llvm: Fix VTX_READ patternsTom Stellard2012-06-013-4/+33
| | | | | | | | | The VTX_READ instructions were using the ADDRParam ComplexPattern which allows a load instruction's offset to be a register, but VTX_READ instructions can only handle an immediate offset. Also, the load_param pattern fragment had an erroneous return true; statement that was causing it to match the wrong load instructions.
* radeon/llvm: Emit 2 bytes for vertex fetch offsetsTom Stellard2012-06-012-1/+3
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* radeon/llvm: Only use indirect (vertex fetch) parameters for kernelsTom Stellard2012-06-011-2/+6
| | | | | | Kernel parameters can only be retrieved via vertex fetchs. Direct parameters (i.e parameters stored in the constant buffer) are not supported yet.
* radeon/llvm: Eliminate CFGStructurizer dependency on AMDIL instructionsTom Stellard2012-06-0111-41/+124
| | | | | | Add some hooks to the R600,SI InstrInfo and RegisterInfo classes, so that the CFGStructurizer pass can run without any relying on AMDIL instructions.
* radeon/llvm: Change prefix on tablegen files to AMDGPUTom Stellard2012-06-0117-50/+50
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* radeon/llvm: Remove deadcode from the R600LowerInstructions passTom Stellard2012-06-011-46/+2
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* radeon/llvm: Remove AMDIL GLOBALSTORE* instructionsTom Stellard2012-06-014-77/+36
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* radeon/llvm: Remove AMDIL GLOBALLOAD* instructionsTom Stellard2012-06-016-128/+24
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* r600g: compute support for evergreenAdam Rak2012-06-0120-12/+2674
| | | | | | | | | Tom Stellard: - Updated for gallium interface changes - Fixed a few bugs: + Set the loop counter + Calculate the correct number of pipes - Added hooks into the LLVM compiler
* clover: Add function for building a clover::module for non-TGSI targets v6Tom Stellard2012-06-013-14/+158
| | | | | | | | | | | | | | | | | | | | | | | | v2: -Separate IR type and LLVM triple -Do the OpenCL C->LLVM IR and linking steps for all PIPE_SHADER_IR types. v3: - Coding style fixes - Removed compatibility code for LLVM < 3.1 - Split build_module_llvm() into three functions: compile(), link(), and build_module_llvm() v4: - Use struct pipe_compute_program v5: - Don't malloc memory for struct pipe_llvm_program v6: - Fix serialization of llvm bytecode Reviewed-by: Francisco Jerez <[email protected]>
* gallium: Add struct pipe_llvm_program_header v3Tom Stellard2012-06-011-0/+8
| | | | | | | | | | | | | | This structure is used as a header that precedes LLVM bytecode programs that are passed to the drivers. v2: - s/pipe_compute_program/pipe_llvm_program/ v3: - Rename to struct pipe_llvm_program_header - Drop the char * prog member Reviewed-by: Francisco Jerez <[email protected]>
* clover: Remove target argument from compile_program_tgsi()Tom Stellard2012-06-013-5/+3
| | | | Reviewed-by: Francisco Jerez <[email protected]>
* clover: Add constructors to some of the module classes v3Tom Stellard2012-06-011-0/+13
| | | | | | | | | | | | This is for the llvm code that can't use extended initializers. v2: - Use const references for vector arguments - Move constructor defs before data members - Initialize all values in the default constructors v3: - Fix typo
* clover: Add necessary flags to libclllvm_la_CXXFLAGSTom Stellard2012-06-011-1/+5
| | | | | | | $(LLVM_CFLAGS) for LLVM defines -DLIBCLC_PATH for libclc path -DCLANG_RESOURCE_DIR for clang includes $(DEFINES) for -DHAVE_LLVM
* clover: Link to the necessary LLVM and Clang libsTom Stellard2012-06-011-1/+17
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* clover: Add a function for retrieving a device's preferred ir v3Tom Stellard2012-06-012-8/+11
| | | | | | | | | | | | | | | | | | | A device now has two function for getting information about the IR it needs to return. ir_format() => returns the preferred IR ir_target() => returns the triple for the target that is understood by clang/llvm. v2: - renamed ir_target() to ir_format() - renamed llvm_triple() to ir_target() v3: - Remove unnecessary include - Do proper conversion from std::vector<char> to std::string Reviewed-by: Francisco Jerez <[email protected]>
* gallium/compute: Add PIPE_COMPUTE_CAP_IR_TARGET v4Francisco Jerez2012-06-012-0/+6
| | | | | | | | | | | | | v2: Tom Stellard - Update CAP description v3: Tom Stellard - TGSI targets should pass an empty string for this CAP. v4: Tom Stellard - TGSI targets can ignore this CAP. Reviewed-by: Francisco Jerez <[email protected]>
* gallium: Add PIPE_SHADER_IR_LLVM to enum pipe_shader_ir v2Tom Stellard2012-06-011-1/+2
| | | | | | | v2: - s/PIPE_SHADER_IR_LLVM_R600/PIPE_SHADER_IR_LLVM/ Reviewed-by: Francisco Jerez <[email protected]>
* svga: fix saturated TEX instructionsBrian Paul2012-05-311-6/+13
| | | | | | | TEX instructions can't do saturation. Do the TEX into a temp reg w/out saturation, then do a MOV_SAT. Reviewed-by: Jakob Bornecrantz <[email protected]>
* scons: add code to generate the various GL API filesBrian Paul2012-05-311-0/+3
| | | | | | | This fixes recent build breakage when we began building the generated API files from xml as part of the normal build process. Fixes http://bugs.freedesktop.org/show_bug.cgi?id=50475
* draw: simplify index buffer specificationBrian Paul2012-05-3114-71/+52
| | | | | Replace draw_set_index_buffer() and draw_set_mapped_index_buffer() with draw_set_indexes() which simply takes a pointer and an index size.
* nv50: hook up forgotten short constant buffer upload methodMarcin Slusarz2012-05-291-0/+1
| | | | Fixes crash in xorg st.
* radeon/llvm: Update and fix some commentsTom Stellard2012-05-292-12/+6
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* radeonsi: Remove use.sgpr* intrinsics, use load instructions insteadTom Stellard2012-05-295-74/+57
| | | | | | | | | | We now model loading uses sgpr values with LLVM IR load instructions that use the USER_SGPR address space. The definition of the sgpr parameter to the use_sgpr() helper function in radeonsi_shader.c has changed so that you can pass raw sgpr values rather than having to divide the sgpr value you want to use by the dword width of the type you want to load.
* radeonsi: Handle TGSI CONST registersTom Stellard2012-05-2912-100/+254
| | | | | We now emit LLVM load instructions for TGSI CONST register reads, which are lowered in the backend to S_LOAD_DWORD* instructions.
* radeon/llvm: Remove AMDILIntrinsicInfo::GetDeclaration fuction bodyTom Stellard2012-05-291-20/+1
| | | | | | | This function was causing compile errors in the tablegen'd code for some intrinsic definitions. I don't think we really need this function, so I'm removing the function body just as a temporary solution. I'll look into removing the entire AMDILIntrinsicInfo class later.
* radeon/llvm: Remove AMDILTargetMachineTom Stellard2012-05-2919-363/+90
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* nouveau: unreference fences on resource destructionChristoph Bumiller2012-05-292-0/+6
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* nvc0: optimize blend cso by checking which by-RT data actually differsChristoph Bumiller2012-05-291-65/+94
| | | | Can save about 200 bytes of command buffer space.
* nvc0: don't upload UCPs if the shader doesn't use themChristoph Bumiller2012-05-291-1/+1
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* nvc0/ir: allow 64-bit constant loads on nve4Christoph Bumiller2012-05-292-1/+3
| | | | Looks like only 128-bit access doesn't work.
* nvc0/ir: fix texture barrier insertion to prevent WAW hazardsChristoph Bumiller2012-05-296-29/+88
| | | | Fixes, for instance, object highlighting in Diablo 3 (wine).
* nvc0/ir: TEX doesn't support JOIN modifier eitherChristoph Bumiller2012-05-291-0/+1
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* gallium: add st_api feature mask to prevent advertising MS visualsChristoph Bumiller2012-05-293-12/+36
| | | | | | | | | | | | | | v2: use a define for the maximum sample count v3: also test odd sample counts (r300 supports MS3) While multisample renderbuffers are supported by mesa, MS visuals are not, so we need a way to tell dri/st not to advertise them even if the gallium driver does support multisampled surfaces. Otherwise applications selecting these non-functional visuals would run into trouble ... Reviewed-by: Brian Paul <[email protected]>
* nv30: Fix generic passing to fragment program in NV34.Roy Spliet2012-05-253-5/+9
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* nv30: handle user index buffersChristoph Bumiller2012-05-254-17/+27
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* radeon/llvm: Use a custom inserter for MASK_WRITETom Stellard2012-05-254-34/+36
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