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* u_blitter: do error checking assertions for shader cachingBrian Paul2014-10-221-21/+30
* radeonsi: implement pipe_rasterizer_state::clip_halfzMarek Olšák2014-10-221-0/+1
* r600g: implement pipe_rasterizer_state::clip_halfzMarek Olšák2014-10-222-0/+2
* r300g: implement pipe_rasterizer_state::clip_halfzMarek Olšák2014-10-223-0/+9
* r600g: Drop references to destroyed blend stateMichel Dänzer2014-10-221-1/+8
* freedreno/a3xx: fix depth/stencil restore formatRob Clark2014-10-211-1/+5
* freedreno/a3xx: fix viewport state during clearRob Clark2014-10-211-1/+19
* freedreno: mark scissor state dirty when enable bit changesRob Clark2014-10-211-0/+10
* freedreno: clear vs scissorRob Clark2014-10-217-13/+96
* clover: Fix build error with LLVM 3.4.Vinson Lee2014-10-211-1/+3
* r600g,radeonsi: convert TGSI shader type to LLVM shader typeMarek Olšák2014-10-211-1/+30
* radeonsi: add some missing register definitionsMarek Olšák2014-10-211-0/+23
* radeonsi: load ring resource descriptors only onceMarek Olšák2014-10-211-35/+42
* radeonsi: clarify shader constant load functionsMarek Olšák2014-10-211-40/+46
* radeonsi: statically declare resource and sampler arraysMarek Olšák2014-10-211-8/+2
* radeonsi: remove conversion of DX9 FACE input to GLMarek Olšák2014-10-211-14/+1
* radeonsi: revert hack for random failures in glsl-max-varyingsMarek Olšák2014-10-211-7/+1
* radeonsi: generate shader pm4 states right after shader compilationMarek Olšák2014-10-213-17/+24
* radeonsi: make pm4 state generation for shaders independent of the contextMarek Olšák2014-10-211-17/+9
* radeonsi: inline si_pm4_alloc_stateMarek Olšák2014-10-214-23/+17
* r300g: replace r300_get_num_samples with a util variantMarek Olšák2014-10-211-25/+1
* gallium: add PIPE_SHADER_CAP_MAX_OUTPUTS and use it in st/mesaMarek Olšák2014-10-2115-0/+32
* vc4: Fix SRC_ALPHA_SATURATE blending.Eric Anholt2014-10-211-3/+11
* vc4: Fix stencil writemask handling.Eric Anholt2014-10-211-2/+2
* vc4: Don't look at back stencil state unless two-sided stencil is enabled.Eric Anholt2014-10-211-2/+6
* freedreno/ir3: add debug flag to disable cpRob Clark2014-10-204-1/+10
* freedreno: positions come out as integers, not half-integersIlia Mirkin2014-10-201-2/+2
* freedreno/a3xx: disable early-z when we have kill'sRob Clark2014-10-203-0/+10
* freedreno/ir3: fix potential gpu lockup with killRob Clark2014-10-204-2/+61
* freedreno/ir3: comment + better fxn nameRob Clark2014-10-201-3/+5
* freedreno/a3xx: only emit dirty constsRob Clark2014-10-202-5/+9
* freedreno/a3xx: more layer/level fixesRob Clark2014-10-203-8/+14
* clover: Don't return CL_INVALID_VALUE if there is no header.EdB2014-10-201-1/+1
* clover: Add allow_empty_tag.EdB2014-10-201-0/+18
* clover: Add initial implementation of clCompileProgram for CL 1.2.EdB2014-10-207-16/+77
* clover: Add a simple compat::pair.EdB2014-10-201-0/+9
* clover/util: Allow using key_equals with pair-like objects other than std::pair.Francisco Jerez2014-10-201-2/+2
* clover/util: Define equality operators for a couple of compat classes.Francisco Jerez2014-10-201-13/+30
* clover/util: Fix construction of compat::vector with a general container as a...Francisco Jerez2014-10-201-2/+4
* vc4: Translate 4-byte index buffers to 2 bytes.Eric Anholt2014-10-194-10/+92
* vc4: Add support for rebasing texture levels so firstlevel == 0.Eric Anholt2014-10-195-3/+83
* vc4: Apply a Newton-Raphson step to improve RSQEric Anholt2014-10-181-2/+20
* vc4: Apply a Newton-Raphson step to improve RCP.Eric Anholt2014-10-181-1/+17
* vc4: Add a little bit more packet parsing to make dump reading easier.Eric Anholt2014-10-181-19/+114
* vc4: Make some assertions about how many flushes/EOFs the simulator sees.Eric Anholt2014-10-174-9/+26
* vc4: Fix accidental dropping of the low bits of the store tilebuffer packet.Eric Anholt2014-10-171-3/+5
* vc4: Set the primitive list format at the start of rendering.Eric Anholt2014-10-172-0/+15
* vc4: Replace the FLUSH_ALL with FLUSH.Eric Anholt2014-10-171-1/+3
* vc4: Add some comments about state management.Eric Anholt2014-10-172-0/+11
* vc4: Make sure there's exactly 1 tile store per tile coords packet.Eric Anholt2014-10-171-15/+64
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