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* nir: Add a nir_opt_undef() to handle csels with undef.Eric Anholt2015-08-141-0/+1
| | | | | | | | | | | | | | | | | | | We may find a cause to do more undef optimization in the future, but for now this fixes up things after if flattening. vc4 was handling this internally most of the time, but a GLB2.7 shader that did a conditional discard and assign gl_FragColor in the else was still emitting some extra code. total instructions in shared programs: 100809 -> 100795 (-0.01%) instructions in affected programs: 37 -> 23 (-37.84%) v2: Use nir_instr_rewrite_src() to update def/use on src[0] (by Thomas Helland). v3: Make sure to flag metadata dirties, and copy the swizzle and abs/neg over to src[0], too (by anholt). Reviewed-by: Thomas Helland <[email protected]> (v2) Tested-by: Thomas Helland <[email protected]> (v2)
* gm107/ir: indirect handle goes first on maxwell alsoIlia Mirkin2015-08-141-8/+4
| | | | | | | Fixes fs-simple-texture-size.shader_test Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.6" <[email protected]>
* nv30: add depth bounds test support for hw that has itIlia Mirkin2015-08-143-2/+14
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50: add depth bounds test supportIlia Mirkin2015-08-143-2/+12
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: add depth bounds test supportIlia Mirkin2015-08-143-2/+9
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* radeonsi: revert a wrong DB bug workaround for VIMarek Olšák2015-08-141-4/+0
| | | | | | | The bug was misunderstood. Besides that, the bug affects a DB feature we don't use yet. Reviewed-by: Michel Dänzer <[email protected]>
* radeon/uvd: implement HEVC supportBoyuan Zhang2015-08-143-17/+298
| | | | | | | | | | | | | add context buffer to fix H265 uvd decode issue. fix H265 corruption issue caused by incorrect assigned ref_pic_list. v2: disable interlace for HEVC add CZ sps flag workaround fix coding style Signed-off-by: Christian König <[email protected]> Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vce: disable VCE dual instance for harvest partLeo Liu2015-08-143-1/+5
| | | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: implement VCE dual instance supportLeo Liu2015-08-143-5/+30
| | | | | | | | | | VCE dual instances are encoding in parallel, it needs two frames for encoding with their own parameters in one IB. Master instance will check the task info to find another frame, assign it to the slave instance Signed-off-by: Leo Liu <[email protected]> Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeon/video: config encode stacked frame number based on HWLeo Liu2015-08-141-0/+2
| | | | | | | | since VCE 3.0 with dual instances, we need stack frames for them. Signed-off-by: Leo Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: make reloc offset signedChristian König2015-08-144-6/+6
| | | | | | | We need a negative offset for FW 50. Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeon/vce: add config task and put task info into encoder v2Leo Liu2015-08-144-33/+47
| | | | | | | | | | | The config task has own task ID, extract the configuration functions into config task. v2 (chk): calculate offset automatically Signed-off-by: Leo Liu <[email protected]> Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeon/vce: fix VCE fail after rebaseLeo Liu2015-08-141-8/+6
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: add dual pipe support for VILeo Liu2015-08-144-22/+21
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: add new firmware support for VI and CILeo Liu2015-08-141-1/+7
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: implement VCE two pipe supportLeo Liu2015-08-143-0/+26
| | | | | | | | v2: rebase by Marek Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/uvd: make 30M as minimum for MPEG4 dpb buffer sizeLeo Liu2015-08-141-0/+2
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/uvd: recalculate dbp buffer sizeLeo Liu2015-08-141-22/+59
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/video: add 4K support for decode/encode parametersLeo Liu2015-08-141-4/+4
| | | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* gallium/radeon: add h264 performance HW decoder supportLeo Liu2015-08-142-22/+43
| | | | | | | | v2: -make tonga use new h264 performance HW decoder; -integrate it scaling buffer to msg_fb buffer Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: use VM for VCEChristian König2015-08-144-20/+44
| | | | | | | | | | v2: (leo) add checking for driver backend v3: (leo) change variable name from use_amdgpu to use_vm v4: rebase by Marek Signed-off-by: Christian König <[email protected]> Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: use VM for UVDChristian König2015-08-141-2/+14
| | | | | | | | | | v2: (leo) add checking for driver backend v3: (leo) change variable name from use_amdgpu to use_vm v4: rebase by Marek Signed-off-by: Christian König <[email protected]> Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: add support for FIJI (v4)Alex Deucher2015-08-144-0/+12
| | | | | | | | | | | | v2: incorporate comments from Marek v3: add missing fiji case in winsys init use tonga raster config (double check this) v4: rebase on harvest patch Reviewed-by: Marek Olšák <[email protected]> (v3) Reviewed-by: Christian König <[email protected]> (v3) Reviewed-by: David Zhang <[email protected]> (v3) Signed-off-by: Alex Deucher <[email protected]>
* winsys/amdgpu: add addrlib support for Fiji (v2)Alex Deucher2015-08-143-1/+11
| | | | | | | | | v2: fix tonga chip check Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: David Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* radeonsi: add harvest support for CI/VI parts (v3)Alex Deucher2015-08-141-92/+116
| | | | | | | | | | | | | Properly calculate the PA_SC_RASTER_CONFIG[_1] settings for harvest chips. v2: - fix default raster config settings for CZ and KV - Suggestions from Michel v3: - handle multiple packers properly for CI+ - GRBM_GFX_INDEX is privileged on VI+ Reviewed-by: Michel Dänzer <[email protected]> (v2) Signed-off-by: Alex Deucher <[email protected]>
* gallium/radeon: enable the GPU load query for amdgpuMarek Olšák2015-08-141-2/+4
| | | | Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: properly handler raster_config setup on CZAlex Deucher2015-08-141-1/+1
| | | | | | | Need to take into account the number of RBs. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
* radeonsi: properly set the raster_config for KVAlex Deucher2015-08-141-5/+9
| | | | | | | | | This enables the second RB on asics that support it which should boost performance. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
* radeonsi: add amdgpu support for querying the GPU reset stateMarek Olšák2015-08-141-1/+14
| | | | Reviewed-by: Christian König <[email protected]>
* radeonsi: add VI hardware supportMarek Olšák2015-08-148-25/+121
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* radeonsi: add definitions for VI status registersMarek Olšák2015-08-141-1/+1079
| | | | | | | | Useful for debugging hangs with the read-register interface. I checked that this adds the same register fields as the kernel driver. Acked-by: Michel Dänzer <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: add VI register definitionsMarek Olšák2015-08-143-62/+1042
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* radeonsi: fix DRM version checks for amdgpu DRM 3.0.0Marek Olšák2015-08-145-11/+19
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* winsys/amdgpu: add addrlib - texture addressing and alignment calculatorMarek Olšák2015-08-1431-7/+22378
| | | | | | | | | This is an internal project that Catalyst uses and now open source will do too. v2: squashed these commits in: - winsys/amdgpu: fix warnings in addrlib - winsys/amdgpu: set PIPE_CONFIG and NUM_BANKS in tiling_flags
* winsys/amdgpu: add a new winsys for the new kernel driverMarek Olšák2015-08-1421-8/+2379
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: - lots of changes according to Emil Velikov's comments - implemented radeon_winsys::read_registers v3: - a lot of new work, many of them adapt to libdrm interface changes Squashed patches: winsys/amdgpu: implement radeon_winsys context support winsys/amdgpu: add reference counting for contexts winsys/amdgpu: add userptr support winsys/amdgpu: allocate IBs like normal buffers winsys/amdgpu: add IBs to the buffer list, adapt to interface changes winsys/amdgpu: don't use KMS handles as reloc hash keys winsys/amdgpu: sync buffer accesses to different rings winsys/amdgpu: use dependencies instead of waiting for last fence v2 gallium/radeon: unify buffer_wait and buffer_is_busy in the winsys interface (amdgpu part) winsys/amdgpu: track fences per ring and be thread-safe winsys/amdgpu: simplify waiting on a variable in amdgpu_fence_wait gallium/radeon: allow the winsys to choose the IB size (amdgpu part) winsys/amdgpu: switch to new amdgpu_cs_query_fence_status interface winsys/amdgpu: handle fence and dependencies merge winsys/amdgpu follow libdrm change to move user fence into UMD winsys/amdgpu: use amdgpu_bo_va_op for va map/unmap v2 winsys/amdgpu: use the new tiling flags winsys/amdgpu: switch to new GTT_USWC definition winsys/amdgpu: expose amdgpu_cs_query_reset_state to drivers winsys/amdgpu: fix valgrind warnings winsys/amdgpu: don't use VRAM with APUs that don't have much of it winsys/amdgpu: require LLVM 3.6.1 for VI because of bug fixes there winsys/amdgpu: remove amdgpu_winsys::num_cpus winsys/amdgpu: align BO size to page size winsys/amdgpu: reduce BO cache timeout winsys/amdgpu: remove useless flushing and waiting in amdgpu_bo_set_tiling winsys/amdgpu: use amdgpu_device_handle as a unique device ID instead of fd winsys/amdgpu: use safer access to amdgpu_fence_wait::signalled winsys/amdgpu: allow maximum IB size of 4 MB winsys/amdgpu: add ip_instance into amdgpu_fence gallium/radeon: add RING_COMPUTE instead of RADEON_FLUSH_COMPUTE winsys/amdgpu: set the ring type at CS initilization winsys/amdgpu: query the GART page size from the kernel winsys/amdgpu: correctly wait for shared buffers to become idle winsys/amdgpu: set the amdgpu_cs_fence structure only once at fence creation winsys/amdgpu: add a specific error message for cs_submit -> -ENOMEM winsys/amdgpu: check num_active_ioctls before calling amdgpu_bo_wait_for_idle winsys/amdgpu: clear user fence BO after allocating it winsys/amdgpu: fix user fences winsys/amdgpu: make amdgpu_winsys_create public winsys/amdgpu: remove thread offloading winsys/amdgpu: flatten the amdgpu_cs_context structure and simplify more v4: require libdrm 2.4.63
* st/vdpau: add HEVC support v2Christian König2015-08-142-3/+139
| | | | | | | v2: fix return code Signed-off-by: Christian König <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* st/omx/enc: stack frame tasks for the gatheringLeo Liu2015-08-142-2/+22
| | | | | | | | Put tasks to the FIFO queue for results Signed-off-by: Leo Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/omx/enc: flush after eos handling v2Leo Liu2015-08-141-0/+1
| | | | | | | | v2 (chk): reorder the flush Signed-off-by: Leo Liu <[email protected]> Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* vl: add HEVC profiles and definesChristian König2015-08-143-2/+120
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* vl: add cap for stacking framesLeo Liu2015-08-141-1/+2
| | | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi: add support for EXT_depth_bounds_testMarek Olšák2015-08-142-5/+7
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* gallium: add an interface for EXT_depth_bounds_testMarek Olšák2015-08-1416-0/+20
| | | | | Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: add support for GLES texture float extensions (v3)Marek Olšák2015-08-1415-0/+34
| | | | | | | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74329 v2: add a CAP for half floats drivers should not expose the CAPs if they don't support the formats v3: update relnotes Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* r600,compute: setup compute sampler states and viewsZoltan Gilian2015-08-145-40/+54
| | | | | | | | v2: Add compute mode flag to sampler state setup (Marek). Drop branches which avoid reference counting (Marek). Simplify unset branch condition (Marek). Reviewed-by: Marek Olšák <[email protected]>
* st/clover: Fix build against LLVM 3.8 SVN r244928Michel Dänzer2015-08-141-0/+2
| | | | | | | | | | | | | | | | | | | | | raw_svector_ostream::flush() is now unnecessary and forbidden: CXX llvm/libclllvm_la-invocation.lo ../../../../../src/gallium/state_trackers/clover/llvm/invocation.cpp: In function 'clover::module {anonymous}::build_module_llvm(llvm::Module*, unsigned int (&)[7])': ../../../../../src/gallium/state_trackers/clover/llvm/invocation.cpp:574:29: error: use of deleted function 'void llvm::raw_svector_ostream::flush()' bitcode_ostream.flush(); ^ In file included from /home/daenzer/src/llvm-git/llvm/include/clang/Basic/VirtualFileSystem.h:22:0, from /home/daenzer/src/llvm-git/llvm/include/clang/Basic/FileManager.h:20, from /home/daenzer/src/llvm-git/llvm/include/clang/Basic/SourceManager.h:38, from /home/daenzer/src/llvm-git/llvm/include/clang/Frontend/CompilerInstance.h:16, from ../../../../../src/gallium/state_trackers/clover/llvm/invocation.cpp:25: /home/daenzer/src/llvm-git/llvm/include/llvm/Support/raw_ostream.h:512:8: note: declared here void flush() = delete; ^ Makefile:862: recipe for target 'llvm/libclllvm_la-invocation.lo' failed Reviewed-by: Francisco Jerez <[email protected]>
* r600g: allow setting geometry shader sampler statesMarek Olšák2015-08-131-5/+0
| | | | | | | | We were ignoring them. This is both hilarious and sad. Cc: [email protected] Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com> Reviewed-by: Alex Deucher <[email protected]>
* r600g: fix polygon offset scaleMarek Olšák2015-08-132-2/+2
| | | | | | | | | | | | The value was copied from r300g, which uses 1/12 subpixels, but this hw uses 1/16 subpixels. Should fix piglit: gl-1.4-polygon-offset (formerly a glean test) (untested, ported from radeonsi) Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com> Reviewed-by: Alex Deucher <[email protected]> Cc: [email protected]
* radeonsi: fix polygon offset scaleMarek Olšák2015-08-131-1/+1
| | | | | | | | | | The value was copied from r300g, which uses 1/12 subpixels, but this hw uses 1/16 subpixels. Fixes piglit: gl-1.4-polygon-offset (formerly a glean test) Reviewed-by: Michel Dänzer <[email protected]> Cc: [email protected]
* radeonsi: enable VS_OUT_MISC_SIDE_BUS_ENAMarek Olšák2015-08-131-0/+1
| | | | | | | This is recommended for better performance. Diag tests always enable this. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: add support for gl_PrimitiveID in the fragment shaderMarek Olšák2015-08-134-9/+49
| | | | | | | | | | It must be obtained from the VS. The GS scenario A must be enabled for PrimID to be generated for the VS. + 4 piglits Reviewed-by: Michel Dänzer <[email protected]>
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