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* radeonsi: use 32_AR for alpha-to-coverage without a color bufferMarek Olšák2016-01-221-1/+1
| | | | | | This avoids the fp16 packing instructions. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add shader conversion code for all SPI color formatsMarek Olšák2016-01-222-14/+140
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: set CB_SHADER_MASK according to SPI color formatsMarek Olšák2016-01-221-16/+35
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use SPI_SHADER_COL_FORMAT fields instead of export_16bpcMarek Olšák2016-01-227-38/+91
| | | | | | | | | | | | | This does change the behavior slightly: If a shader writes COLOR[i] and that color buffer isn't bound, the shader will export MRT_NULL instead and discard the IR tree that calculates the output. The only exception is alpha-to-coverage, which requires an alpha export. v2: - update a comment about 16BPC - account for MRTZ when when fixing alpha-test/kill Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't enable blending if colormask == 0Marek Olšák2016-01-221-0/+3
| | | | | | most likely useless, but doesn't hurt Reviewed-by: Nicolai Hähnle <[email protected]>
* targets/dri: android: use WHOLE static librariesEmil Velikov2016-01-221-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | By using whole static libraries the android buildsystem provides whole-archive (alike) solution. This means that we don't need to worry about the order of the static libraries and any reverse, recursive or circular dependencies that they have between one another. Without this the linker will discard any unused hunks of one library and we'll end up with unresolved symbols as those are required by another static library. This issue has become more prominent with the introduction of pipe-loader. Whole static libraries has been used in i915/i965 for a very long time, so we might do the same. v2: - Better commit message (Ilia) - Keep external dependencies as [normal] static libs (Mauro) Cc: [email protected] Cc: Mauro Rossi <[email protected]> Reported-by: Mauro Rossi <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* freedreno/a4xx: Add support for adreno 430cstout2016-01-211-0/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: make opc array static constChristian Gmeiner2016-01-211-1/+1
| | | | | Signed-off-by: Christian Gmeiner <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno: implement emit_string_markerRob Clark2016-01-212-1/+28
| | | | | | Writes string to cmdstream in payload of a no-op packet. Signed-off-by: Rob Clark <[email protected]>
* gallium: add GREMEDY_string_markerRob Clark2016-01-2116-0/+22
| | | | | | | | | | Since the GREMEDY extensions are normally only exposed by the gremedy debugger (and could possibly trigger debug paths in the app), we don't expose the extension by default, but instead only with ST_DEBUG=gremedy. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* r600g: don't leak driver const buffersGrazvydas Ignotas2016-01-211-0/+6
| | | | | | | | | | | The buffers are referenced from r600_update_driver_const_buffers() -> r600_set_constant_buffer() -> u_upload_data(), but nothing ever releases the reference. Similar case with driver_consts. Found using valgrind. Signed-off-by: Grazvydas Ignotas <[email protected]> Cc: <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* nv50/ir: 64-bit splitting fixesIlia Mirkin2016-01-201-1/+2
| | | | | | | Take reading shader outputs into account, and use setFlagsDef for the carry since we rely on having i->flagsDef being set. Signed-off-by: Ilia Mirkin <[email protected]>
* gk110/ir: allow carry to be set/read by imadIlia Mirkin2016-01-201-0/+4
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gm107/ir: add carry emission to LOP and IADDIlia Mirkin2016-01-201-0/+4
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gm107/ir: add ATOM and CCTL supportIlia Mirkin2016-01-201-0/+52
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gm107/ir: set LD/ST address width bitIlia Mirkin2016-01-201-0/+2
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gk110/ir: fix double-wide vm addressIlia Mirkin2016-01-201-0/+4
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* gk110/ir: add OP_CCTL handlingIlia Mirkin2016-01-201-0/+35
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* gk110/ir: add atomic op emission, fix gmem loadsIlia Mirkin2016-01-201-5/+65
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* llvmpipe: warn about illegal use of objects in different contextsRoland Scheidegger2016-01-213-1/+32
| | | | | | | | | | | Doing that is clearly a bug. We can't quite assert as st/mesa may hit this, but increase at least visibility of it a bit. (For the non-refcounted objects it would be illegal too, but we can't detect that unless we'd store the context ourselves. Plus, those don't tend to cause random crashes at context or object destruction time... So just sampler views, surfaces and so targets for now.) Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe,i915: add back NEW_RASTERIZER dependency when computing vertex infoRoland Scheidegger2016-01-213-3/+11
| | | | | | | | | | | | | | | | | | | | I removed this mistakenly in 2dbc20e45689e09766552517a74e2270e49817b5. I actually thought it should not be necessary and a piglit run didn't show any differences, but this shouldn't have been in there. draw_prepare_shader_outputs() is in fact dependent on NEW_RASTERIZER. The new polygon-mode-facing test indeed shows why this is necessary, there's lots of invalid reads and writes with valgrind (also crashes without valgrind), because the pre-pipeline vertex size doesn't match the post-pipeline vertex size (note this won't help much with stages which don't have the prepare hook which can grow the vertex size, in particular the wide point stage, but this isn't used by llvmpipe). The test still won't pass, of course, but it is only usage of uninitialized values now, which is much less dangerous... (Albeit I'm pretty sure for i915 it really is not needed anymore as it doesn't care about the extra outputs and doesn't call draw_prepare_shader_outputs().) Reviewed-by: Jose Fonseca <[email protected]>
* nv50/ir: don't flip SHL(ADD) into ADD(SHL) if ADD sources have modifiersIlia Mirkin2016-01-201-0/+2
| | | | | Fixes: 31fde8fa (nv50/ir: flip shl(add, imm) into add(shl, imm)) Signed-off-by: Ilia Mirkin <[email protected]>
* gk110/ir: fix load from shared memoryIlia Mirkin2016-01-201-1/+1
| | | | | | It was accidentally using the store opcode. Signed-off-by: Ilia Mirkin <[email protected]>
* gk110/ir: add partial BAR supportIlia Mirkin2016-01-201-2/+18
| | | | | | This is enough for the plain TGSI BARRIER implementation. Signed-off-by: Ilia Mirkin <[email protected]>
* llvmpipe: turn depth clears into full depth/stencil clears for d24x8 formatsRoland Scheidegger2016-01-201-11/+14
| | | | | | | | | | | | If we have a d24x8 format, there is no stencil. Therefore, we can always clear these bits too, which means this will be some kind of memset rather than read-modify-write. This is good for some 7% increase or so in gears with huge window size - seems to have a bigger effect if things aren't in caches. Of course, any real app won't spend nearly as much time comparatively in clearing depth buffer in the first place, so the speedup will be much lower. Reviewed-by: Jose Fonseca <[email protected]>
* st/va: fix motion adaptive deinterlacingChristian König2016-01-191-1/+1
| | | | Signed-off-by: Christian König <[email protected]>
* util/u_pstipple.c: copy immediates during transformationNicolai Hähnle2016-01-191-0/+1
| | | | | | | | | | | Apparently, nobody has combined stippling with a fragment shader containing immediates in almost five years... Fixes a bug in Kodi with radeonsi reported by Christian König. Cc: "11.0 11.1" <[email protected]> Tested-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nv50/ir: swap the least-ref'd source into src1 when both const/immIlia Mirkin2016-01-181-10/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The whole point of inlining sources is to reduce loads. We can end up in a situation where one value is used a lot of times, and one value is used only once per instruction. The once-per-instruction one is the one that should get inlined, but with the previous algorithm, it was given no preference. This flips things around to preferring putting less-referenced values into src1 which increases the likelihood of them being inlined. While we're at it, adjust the heuristic to not treat 0 as an immediate, as well as (effectively) check for situations where LIMMs can't be loaded. All this yields improvements on nvc0: total instructions in shared programs : 6261157 -> 6255985 (-0.08%) total gprs used in shared programs : 945082 -> 943417 (-0.18%) total local used in shared programs : 30372 -> 30288 (-0.28%) total bytes used in shared programs : 50089256 -> 50047880 (-0.08%) local gpr inst bytes helped 21 822 3332 3332 hurt 0 278 565 565 And more importantly avoids generating really bad code with SSBOs, where we end up checking a lot of different values (usually immediates) against the length. On nv50 we get comparable results, and even improve packing (bytes went down more than instructions): total instructions in shared programs : 6346564 -> 6341277 (-0.08%) total gprs used in shared programs : 728719 -> 725131 (-0.49%) total local used in shared programs : 3552 -> 3552 (0.00%) total bytes used in shared programs : 43995688 -> 43932928 (-0.14%) local gpr inst bytes helped 0 1380 3252 3774 hurt 0 287 1710 1365 Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a4xx: use smaller threadsize for more registersRob Clark2016-01-181-2/+5
| | | | | | | | Once we go past half of the "GPR" register file, it seems like we need to run frag shader with smaller threadsize. (The vertex shader already runs at TWO_QUADS, which is the minimum.) Signed-off-by: Rob Clark <[email protected]>
* freedreno: per-generation OUT_IB packetRob Clark2016-01-189-6/+43
| | | | | | | | | | Some a4xx firmware doesn't implement the "PFD" (prefetch-disabled) version of the CP_INDIRECT_BUFFER packet. So allow for PFD vs PFE per generation. Switch a3xx and a4xx over to using prefetch-enabled version (which is also what blob does.. it seems only on a2xx we cannot use PFE). Signed-off-by: Rob Clark <[email protected]>
* gallium: bundle the compat header u_pwr8.h in the tarballEmil Velikov2016-01-181-0/+1
| | | | Signed-off-by: Emil Velikov <[email protected]>
* st/va: add motion adaptive deinterlacing v2Christian König2016-01-184-7/+82
| | | | | | v2: minor cleanup Signed-off-by: Christian König <[email protected]>
* gallium/radeon: Rename do_invalidate_resource to invalidate_bufferMichel Dänzer2016-01-181-4/+6
| | | | | | | And only call it from r600_invalidate_resource for buffer resources. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/dri: Don't call invalidate_resource for NULL depth/stencil buffersMichel Dänzer2016-01-181-2/+4
| | | | | | | Fixes crash in 4 EGL piglit tests with radeonsi. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Avoid warning about LLVM generating R_0286D0_SPI_PS_INPUT_ADDRMichel Dänzer2016-01-181-0/+3
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Print "LLVM emitted unknown config register" warning only onceMichel Dänzer2016-01-181-2/+9
| | | | | | | Say "LLVM" instead of "Compiler" for clarity. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* llvmpipe: use vpkswss when dst is signedOded Gabbay2016-01-181-16/+15
| | | | | | | | | | | | | | | | | | | This patch fixes a bug when building a pack instruction. For POWER (altivec), in case the destination is signed and the src width is 32, we need to use vpkswss. The original code used vpkuwus, which emits an unsigned result. This fixes the following piglit tests on ppc64le: - spec@arb_color_buffer_float@gl_rgba8-drawpixels - shaders@glsl-fs-fogscale I've also corrected some coding style issues in the function. v2: Returned else statements to vmware style Signed-off-by: Oded Gabbay <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gm107/ir: don't do indirect frag shader inputs on GM107Ilia Mirkin2016-01-171-0/+1
| | | | | | | | Apparently the IPA op decided to stop working with offsets. Need to figure out if we need to do an AL2P situation or something similar. For now just turn it back off. Signed-off-by: Ilia Mirkin <[email protected]>
* tgsi: initialize Atomic field in tgsi_default_declarationIlia Mirkin2016-01-171-0/+1
| | | | | | | | Spotted by Coverity. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nvc0: bsp_bo can't be nullIlia Mirkin2016-01-171-1/+1
| | | | | | | We already deref it earlier. And these are all allocated on load. Spotted by Coverity. Signed-off-by: Ilia Mirkin <[email protected]>
* llvmpipe: fix arguments order given to vec_andcOded Gabbay2016-01-172-1/+7
| | | | | | | | | | | | | | | | This patch fixes a classic "confuse the enemy" bug. _mm_andnot_si128 (SSE) and vec_andc (VMX) do the same operation, but the arguments are opposite. _mm_andnot_si128 performs "r = (~a) & b" while vec_andc performs "r = a & (~b)" To make sure this error won't return in another place, I added a wrapper function, vec_andnot_si128, in u_pwr8.h, which makes the swap inside. Signed-off-by: Oded Gabbay <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* freedreno/ir3: fix mad 3rd src delay calcRob Clark2016-01-171-1/+1
| | | | | | | In fad158a0 ("freedreno/ir3: array rework") the src # (n) shifted by one, but missed updating delay-slot calc. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: better array register allocationRob Clark2016-01-162-9/+51
| | | | | | | Detect arrays which don't conflict with each other and allow overlapping register allocation. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: array offset can be negativeRob Clark2016-01-165-12/+13
| | | | | | | | | | | | | | | | | | | | | | It at least happens with some piglit tests, like $piglit/bin/vp-address-01 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL CONST[0..7] DCL ADDR[0] 0: ARL ADDR[0].x, IN[1].xxxx 1: MOV_SAT OUT[1], CONST[ADDR[0].x-1] 2: DP4 OUT[0].x, CONST[4], IN[0] 3: DP4 OUT[0].y, CONST[5], IN[0] 4: DP4 OUT[0].z, CONST[6], IN[0] 5: DP4 OUT[0].w, CONST[7], IN[0] 6: END Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: workaround bug/featureRob Clark2016-01-161-0/+9
| | | | | | | | | | Seems like in certain cases, we cannot use c<a0.x+0> as the third src to cat3 instructions. This may be slightly conservative, we may only have this restriction when the first src is also const. This fixes, for example, +24/-0 of the variable-indexing piglit tests. Signed-off-by: Rob Clark <[email protected]>
* ttn: use writemask for store_varRob Clark2016-01-161-26/+2
| | | | | | | Only user is freedreno, and after array-rework it can cope. Avoids generating loads for a store. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: array reworkRob Clark2016-01-169-363/+365
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: refactor/simplify cpRob Clark2016-01-161-87/+82
| | | | | | | | | If we handle separately the special case of eliminating output mov (which includes keeps and various other cases where we don't have a consuming instruction's src register to collapse things into), we can simplify the logic. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix incorrect decoding of mov instructionsRob Clark2016-01-161-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: remove unused tgsi tokens ptrRob Clark2016-01-161-1/+0
| | | | Signed-off-by: Rob Clark <[email protected]>
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