summaryrefslogtreecommitdiffstats
path: root/src/gallium
Commit message (Collapse)AuthorAgeFilesLines
* gallium: add double opcodes and TGSI execution (v4.2)Dave Airlie2015-02-204-30/+876
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for a set of double opcodes to TGSI. It is an update of work done originally by Michal Krol on the gallium-double-opcodes branch. The opcodes have a hint where they came from in the header file. v2: add unsigned/int <-> double v2.1: update docs. v3: add DRSQ (Glenn), fix review comments (Glenn). v4: drop DDIV v4.1: cleanups, fix some docs bugs, (Ilia) rework store_dest and fetch_source fns. (Ilia) 4.2: fixup float comparisons (Ilia) This is based on code by Michael Krol <[email protected]> Roland and Glenn also reviewed earlier versions. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallium/util: indentation fixBrian Paul2015-02-191-3/+3
|
* freedreno: add missing PIPE_CAP_RESOURCE_FROM_USER_MEMORY to switchIlia Mirkin2015-02-191-0/+1
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: add ARB_instanced_arrays supportIlia Mirkin2015-02-192-2/+3
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: add support for vertexid and instanceid sysvalsIlia Mirkin2015-02-194-16/+119
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno: pass number of instances to drawIlia Mirkin2015-02-198-18/+22
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: add ETC2 decoding supportIlia Mirkin2015-02-192-4/+17
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* llvmpipe,softpipe: only support ETC1, not the upcoming ETC2Ilia Mirkin2015-02-182-0/+8
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gallium: add ETC2 format supportIlia Mirkin2015-02-187-114/+104
| | | | | | | No actual decoding is added, similar faking mechanism to bptc. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* freedreno/a3xx: add hardware ETC1 supportIlia Mirkin2015-02-182-0/+4
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gallium/dri: Shut up a compiler warning.Eric Anholt2015-02-181-1/+1
| | | | | | | The compiler doesn't see that buffers is set in the !image case and used in the !image case. Reviewed-by: Matt Turner <[email protected]>
* ilo: fix PCB alloc asserts on Gen7.5 GT3Chia-I Wu2015-02-181-1/+5
| | | | GT3 has two slices and all limits are doubled.
* ilo: fix compiler warningsChia-I Wu2015-02-183-8/+12
| | | | | Fix -Wmaybe-uninitialized warnings. The change to ilo_blit_resolve_slices_for_hiz() is a potential bug fix.
* auxiliary/vl: honour the DRI2PROTO_CFLAGSEmil Velikov2015-02-181-0/+1
| | | | | | | | Otherwise for non-default installations the build will fail to find the headers and error out. Cc: "10.5" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* auxiliary/vl: Build vl_winsys_dri.c only when needed.Emil Velikov2015-02-181-0/+4
| | | | | | | | | | | | With commit c39dbfdd0f7(auxiliary/vl: bring back the VL code for the dri targets) we did not fully consider users of dri-swrast alone. Thus we ended up trying to compile the dri2 specific code on platform which lack it - Cygwin for example. Cc: "10.5" <[email protected]> Reported-by: Jon TURNEY <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Jon TURNEY <[email protected]>
* Revert "radeon/llvm: enable unsafe math for graphics shaders"Michel Dänzer2015-02-181-4/+0
| | | | | | | | | | | This reverts commit 0e9cdedd2e3943bdb7f3543a3508b883b167e427. It caused the grass to disappear in The Talos Principle. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89069 Cc: "10.5 10.4" <[email protected]> Reviewed-by: Tom Stellard <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g/sb: treat undefined values like constantsDave Airlie2015-02-181-2/+2
| | | | | | | | | | | | When we schedule an instructions with undefined value, we eventually will use 0, which is a constant, however sb wasn't taking this into account and creating ops with illegal scalar swizzles. this replaces my fix for op3 in t slots. Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i915g: Use the actual MIN instruction.Kenneth Graunke2015-02-171-15/+1
| | | | | | | | | | | | | Matt Turner noticed that the hardware has always had a MIN instruction, but the driver always used MAX+MOV for no apparent reason. This should cut an instruction, and a temporary, allowing more programs to run in hardware. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* radeonsi: fix a crash if a stencil ref state is set before a DSA stateMarek Olšák2015-02-171-4/+8
| | | | | | | | | | | | + minor indentation fixes Discovered by Axel Davy. This can't be reproduced with any app, because all state trackers set a DSA state first. Cc: 10.5 10.4 10.3 <[email protected]> Reviewed-by: Axel Davy <[email protected]>
* r600g,radeonsi: implement GL_AMD_pinned_memoryMarek Olšák2015-02-175-4/+54
| | | | | | v2: update release notes Reviewed-by: Christian König <[email protected]>
* winsys/radeon: test the userptr ioctl to see if it's presentMarek Olšák2015-02-175-19/+35
| | | | | | There is no other way to check for support. Reviewed-by: Christian König <[email protected]>
* winsys/radeon: allow unaligned size for user-memory buffersMarek Olšák2015-02-171-1/+1
| | | | | | This is not required, but being user-friendly doesn't hurt. Reviewed-by: Christian König <[email protected]>
* winsys/radeon: allow mapping a user bufferMarek Olšák2015-02-173-2/+8
| | | | | | OpenGL requires this. Reviewed-by: Christian König <[email protected]>
* gallium: add interface and state tracker support for GL_AMD_pinned_memoryMarek Olšák2015-02-1713-0/+25
| | | | | | v2: add alignment restrictions to docs, fix indentation in headers Reviewed-by: Christian König <[email protected]>
* winsys/radeon: add user pointer supportChristian König2015-02-172-0/+113
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: initialize TC_L2_dirty to false after buffer allocationMarek Olšák2015-02-171-0/+1
| | | | | | I forgot to do this, though "true" should have no effect on correctness. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: small fix in SPI stateMarek Olšák2015-02-171-2/+4
| | | | | Cc: 10.5 10.4 <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: use fences to implement PIPE_QUERY_GPU_FINISHEDMarek Olšák2015-02-171-9/+13
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89014 Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: demote TIMESTAMP_DISJOINT query to be a software queryMarek Olšák2015-02-171-14/+13
| | | | | | The query result is always constant. Reviewed-by: Michel Dänzer <[email protected]>
* ilo: always set up BLEND_STATE on Gen8Chia-I Wu2015-02-171-7/+1
| | | | There is now an DW0 that seems to be always referenced.
* ilo: fix alpha test on Gen8Chia-I Wu2015-02-171-5/+26
| | | | | Shoudl use GEN8_BLEND_DW0_ALPHA_TEST_ENABLE instead of GEN6_RT_DW1_ALPHA_TEST_ENABLE (and others).
* ilo: fix some state pointer commands on Gen8Chia-I Wu2015-02-151-0/+20
| | | | | | 3DSTATE_CC_STATE_POINTERS seems to be ignored when bit 0 of DW1 is not set. Follow i965 and set the bit for 3DSTATE_CC_STATE_POINTERS and 3DSTATE_BLEND_STATE_POINTERS. Add gen checks for all state pointer commands.
* nvc0: allow holes in xfb target listsIlia Mirkin2015-02-142-4/+13
| | | | | | | | Tested with a modified xfb-streams test which outputs to streams 0, 2, and 3. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.4 10.5" <[email protected]>
* nvc0: bail out of 2d blits with non-A8_UNORM alpha formatsIlia Mirkin2015-02-141-2/+5
| | | | | | | | This fixes the teximage-colors uploads with GL_ALPHA format and non-GL_UNSIGNED_BYTE type. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.4 10.5" <[email protected]>
* clover: Use Legacy PassManager for LLVM trunk (3.7)Shawn Starr2015-02-141-0/+9
| | | | | Reviewed-by: Tom Stellard <[email protected]> Signed-off-by: Shawn Starr <[email protected]>
* ilo: fix JIP/UIP on Gen8Chia-I Wu2015-02-142-9/+25
| | | | UIP is in DW2 and JIP is in DW3 on Gen8. Also, the units are in bytes.
* ilo: do not set GEN6_THREADCTRL_SWITCHChia-I Wu2015-02-141-4/+0
| | | | It is not needed on Gen6+, and it appears to be broken on Gen8.
* ilo: correct ISA UIP/JIP decoding for Gen8Chia-I Wu2015-02-141-18/+39
| | | | JIP is int32_t and UIP is in DW2 on Gen8.
* ilo: prepare for 64-bit immediates decodingChia-I Wu2015-02-141-15/+31
| | | | Replace imm32 by imm64. Add more ways (UD, D, etc) to access the immediate.
* ilo: cleanup ISA DW1 decodingChia-I Wu2015-02-141-34/+55
| | | | Decode the higher and lower 16 bits separately.
* ilo: cleanup ISA DW0 decodingChia-I Wu2015-02-141-10/+16
| | | | | Add disasm_inst_decode_dw0_opcode_gen6() to decode the opcode. Simplify branch_ctrl/acc_wr_ctrl decoding.
* ilo: update some outdated gen checksChia-I Wu2015-02-141-4/+4
| | | | | | Update gen checks for 3DSTATE_POLY_STIPPLE_OFFSET, 3DSTATE_POLY_STIPPLE_PATTERN, 3DSTATE_LINE_STIPPLE, and 3DSTATE_AA_LINE_PARAMETERS.
* ilo: fix rectlist length on Gen8Chia-I Wu2015-02-141-1/+1
| | | | 5 PIPE_CONTROLs, 2 3DSTATE_WM_HZ_OP, and depth buffer setup require 65 DWords.
* ilo: fix 3DSTATE_VF_TOPOLOGYChia-I Wu2015-02-141-2/+1
| | | | The pipe primitive type was wrongly translated twice.
* os,llvmpipe: Set rasterizer thread names on Linux.Jose Fonseca2015-02-132-1/+18
| | | | | | | | | | | To help identify llvmpipe rasterizer threads -- especially when there can be so many. We can eventually generalize this to other OSes, but for that we must restrict the function to be called from the current thread. See also http://stackoverflow.com/a/7989973 Reviewed-by: Roland Scheidegger <[email protected]>
* vc4: Make SF be a flag on the QIR instructions.Eric Anholt2015-02-128-51/+47
| | | | | | | | | | | | Right now the places that used to emit a mov.sf just put the SF on the previous instruction when it generated the source of the SF value. Even without optimization to push the sf up further (and kill thus potentially kill more MOVs), this gets us: total uniforms in shared programs: 13455 -> 13457 (0.01%) uniforms in affected programs: 3 -> 5 (66.67%) total instructions in shared programs: 40296 -> 40198 (-0.24%) instructions in affected programs: 12595 -> 12497 (-0.78%)
* auxiliary/vl: bring back the VL code for the dri targetsEmil Velikov2015-02-128-6/+25
| | | | | | | | | | | | | | | | | With commit c642e87d9f4(auxiliary/vl: rework the build of the VL code) we split out the VL code into a separate static library that was meant to be used by the VL targets alone - va, vdpau, xvmc. The commit failed to consider the way we handle vdpau-gl interop and broke it. Bring back the functionality by keeping the vl <> vl_stub separation as requrested by Christian. v2: Update the omx target as well. Update mesa-stable email address. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86837 Cc: "10.5" <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Tested-by: Andy Furniss <[email protected]>
* ilo: update screen init for Gen8Chia-I Wu2015-02-121-8/+32
| | | | | This is very preliminary and is only tested with glxgears. All information about Gen8 is derived from i965 and beignet.
* ilo: update outdated render command emissions for Gen8Chia-I Wu2015-02-121-4/+4
|
* ilo: update rectlist command emission for Gen8Chia-I Wu2015-02-124-7/+93
|
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 10:19:38 +0000