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* gallium/u_threaded: mark queries flushed only for non-deferred flushesNicolai Hähnle2017-11-092-4/+6
* radeonsi: move fence functions to si_fence.cNicolai Hähnle2017-11-096-267/+312
* winsys/amdgpu: handle cs_add_fence_dependency for deferred/unsubmitted fencesNicolai Hähnle2017-11-094-12/+41
* gallium: add PIPE_FLUSH_{TOP,BOTTOM}_OF_PIPE bitsNicolai Hähnle2017-11-092-0/+16
* gallium: add PIPE_FLUSH_ASYNC and PIPE_FLUSH_HINT_FINISHNicolai Hähnle2017-11-093-1/+18
* gallium: remove unused and deprecated u_time.hNicolai Hähnle2017-11-098-157/+1
* util: move os_time.[ch] to src/utilNicolai Hähnle2017-11-0955-380/+53
* radeonsi: always use async compiles when creating shader/compute statesNicolai Hähnle2017-11-092-34/+50
* radeonsi: fix potential use-after-free of debug callbacksNicolai Hähnle2017-11-091-0/+4
* radeonsi: move pipe debug callback to si_contextNicolai Hähnle2017-11-096-19/+19
* util: move pipe_barrier into src/util and rename to util_barrierNicolai Hähnle2017-11-094-88/+13
* gallium: add async debug message forwarding helperNicolai Hähnle2017-11-094-0/+192
* gallium: clarify the constraints on sampler_view_destroyNicolai Hähnle2017-11-092-6/+20
* radeonsi: reduce the scope of sel->mutex in si_shader_select_with_keyNicolai Hähnle2017-11-091-4/+4
* radeonsi: use ready fences on all shaders, not just optimized onesNicolai Hähnle2017-11-093-26/+67
* r600g: use SIMPLE_FLOAT for blending to enable some optimizationsIlia Mirkin2017-11-082-0/+2
* nv50: make blending work so that zero wins in a multiplicationIlia Mirkin2017-11-081-0/+5
* amdgpu: use simple mtxTimothy Arceri2017-11-095-44/+45
* mesa: use simple mtx in core mesaTimothy Arceri2017-11-091-11/+11
* broadcom/vc5: Add vc5_drm.h to the release tarballAndreas Boll2017-11-081-0/+1
* clover: use the unified check for c++11 instead of the gcc version numberGert Wollny2017-11-081-3/+3
* swr: Replace the check for c++11 by the unified versionGert Wollny2017-11-081-2/+2
* targets/opencl: don't hardcode the icd file install to /etc/...Emil Velikov2017-11-081-1/+1
* gallivm: Use new LLVM fast-math-flags APITobias Droste2017-11-081-0/+4
* amd/addrlib: update to latest versionMarek Olšák2017-11-081-1/+0
* braodcom/vc5: Flush the job when it grows over 1GB.Eric Anholt2017-11-073-0/+10
* broadcom/vc5: Fix pausing of transform feedback.Eric Anholt2017-11-071-1/+1
* broadcom/vc5: Add support for GL_RASTERIZER_DISCARDEric Anholt2017-11-071-0/+2
* broadcom/vc5: Add partial transform feedback query support.Eric Anholt2017-11-073-17/+64
* broadcom/vc5: Add occlusion query support.Eric Anholt2017-11-076-20/+121
* broadcom/vc5: Skip emitting textures that aren't used.Eric Anholt2017-11-071-2/+4
* broadcom/vc5: Add missing SRGBA8 ETC2 support.Eric Anholt2017-11-071-0/+1
* broadcom/vc5: Disable early Z test when the FS writes Z.Eric Anholt2017-11-071-1/+2
* broadcom/vc5: Shift the min/max lod fields by the BASE_LEVEL.Eric Anholt2017-11-072-4/+15
* broadcom/vc5: Add support for anisotropic filtering.Eric Anholt2017-11-071-0/+9
* broadcom/vc5: Fix mipmap filtering enums.Eric Anholt2017-11-071-6/+8
* broadcom/vc5: Fix height padding of small UIF slices.Eric Anholt2017-11-071-1/+5
* broadcom/vc5: Print the actual offsets in HW for our resource layout debug.Eric Anholt2017-11-071-34/+55
* broadcom/vc5: Set the available VS outputs to match the FS inputs.Eric Anholt2017-11-071-1/+4
* broadcom/vc5: Set the max texture LOD bias.Eric Anholt2017-11-071-1/+1
* broadcom/vc5: Fix translation of stencil ops.Eric Anholt2017-11-072-8/+30
* broadcom/vc5: Move stencil state packing to the CSO.Eric Anholt2017-11-073-27/+47
* broadcom/vc5: Introduce a helper for pre-packing our V3DXX structs.Eric Anholt2017-11-072-165/+155
* broadcom/vc5: Add a cl_emit() variant for merging with a pre-packed struct.Eric Anholt2017-11-072-19/+29
* broadcom/vc5: Skip emitting depth offset while disabled.Eric Anholt2017-11-071-1/+4
* broadcom/vc5: Don't emit stencil config if not doing stencil test.Eric Anholt2017-11-071-1/+2
* broadcom/vc5: Don't emit updated blend factors/funcs while disabled.Eric Anholt2017-11-071-1/+5
* broadcom/vc5: Make sure the TMU indirect struct is appropriately aligned.Eric Anholt2017-11-071-0/+2
* broadcom/vc5: Use DEPTH24_STENCIL8 for rendering to depth-only textures.Eric Anholt2017-11-071-1/+1
* radeonsi: add si_screen::has_ls_vgpr_init_bugMarek Olšák2017-11-074-3/+5
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