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* meson: Add support for the vc5 driver.Eric Anholt2017-10-174-2/+111
| | | | | | | v2: Default vc5 to off, since it requires the simulator currently. Add missing dep on the XML generation from libbroadcom_vc5. Reviewed-by: Dylan Baker <[email protected]> (v1)
* meson: Add support for the pl111 driver.Eric Anholt2017-10-173-1/+38
| | | | Reviewed-by: Dylan Baker <[email protected]>
* meson: Add support for the vc4 driver.Eric Anholt2017-10-174-2/+146
| | | | Reviewed-by: Dylan Baker <[email protected]>
* radeonsi: if there's just const buffer 0, set it in place of CONST/SSBO pointerMarek Olšák2017-10-174-13/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SI_SGPR_CONST_AND_SHADER_BUFFERS now contains the pointer to const buffer 0 if there is no other buffer there. Benefits: - there is no constbuf descriptor upload and shader load It's assumed that all constant addresses are within bounds. Non-constant addresses are clamped against the last declared CONST variable. This only works if the state tracker ensures the bound constant buffer matches what the shader needs. Once we get 32-bit pointers, we can only do this for user constant buffers where the driver is in charge of the upload so that it can guarantee a 32-bit address. The real performance benefit might not be measurable. These apps get 100% theoretical benefit in all shaders (except where noted): - antichamber - barman arkham origins - borderlands 2 - borderlands pre-sequel - brutal legend - civilization BE - CS:GO - deadcore - dota 2 -- most shaders - europa universalis - grid autosport -- most shaders - left 4 dead 2 - legend of grimrock - life is strange - payday 2 - portal - rocket league - serious sam 3 bfe - talos principle - team fortress 2 - thea - unigine heaven - unigine valley -- also sanctuary and tropics - wasteland 2 - xcom: enemy unknown & enemy within - tesseract - unity (engine) Changed stats only: SGPRS: 2059998 -> 2086238 (1.27 %) VGPRS: 1626888 -> 1626904 (0.00 %) Spilled SGPRs: 7902 -> 7865 (-0.47 %) Code Size: 60924520 -> 60982660 (0.10 %) bytes Max Waves: 374539 -> 374526 (-0.00 %) Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: clean up ac_build_indexed_load function interfacesMarek Olšák2017-10-172-19/+19
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: handle 64-bit loads earlier in fetch_constantMarek Olšák2017-10-171-16/+10
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add si_descriptors::gpu_address and remove buffer_offsetMarek Olšák2017-10-173-14/+18
| | | | | | This allows us to change the pointer arbitrarily. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: unify code for extracting a buffer address from a descriptorMarek Olšák2017-10-171-4/+7
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove atom parameter from si_upload_descriptorsMarek Olšák2017-10-171-8/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: pack si_descriptors better againMarek Olšák2017-10-171-2/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: emit dirty consecutive pointers in one SET_SH_REG packetMarek Olšák2017-10-171-27/+39
| | | | | | IB size: -1.6% Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: split si_emit_shader_pointerMarek Olšák2017-10-171-11/+23
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: generalize the SI_VS_SHADER_POINTER_MASK macroMarek Olšák2017-10-173-4/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: use SPI_SHADER_USER_DATA_COMMONMarek Olšák2017-10-171-13/+13
| | | | | | IB size: -0.4% Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: move RW_BUFFERS from s[0:1] to s[8:9] for HS and GSMarek Olšák2017-10-172-39/+16
| | | | | | | Let's use the same user data SGPRs in all stages. (for SPI_SHADER_USER_DATA_COMMON_0) Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add GFX-IB-size query to the HUDMarek Olšák2017-10-177-0/+11
| | | | | | It shows the sum of all IBs per frame. Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: disable CPU caching for GFX & SDMA IBsMarek Olšák2017-10-171-4/+9
| | | | | | This should decrease IB fetch latency. Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: don't do read-modify-write on command buffersMarek Olšák2017-10-172-4/+16
| | | | | | i.e. don't use |= Reviewed-by: Nicolai Hähnle <[email protected]>
* broadcom/vc4: Fix false-positive for the tiling ioctls on simulator mode.Eric Anholt2017-10-171-0/+1
| | | | | If there happened to be an ENOENT laying around, we would try using the ioctls later and fail out resource allocation.
* broadcom/vc4: Skip BO labeling when in simulator mode.Eric Anholt2017-10-172-1/+5
| | | | | It was calling down into i915 trying to label the BO, which is definitely not the right thing.
* broadcom/vc5: Don't forget to set the RT format for 1555 textures.Eric Anholt2017-10-171-2/+2
| | | | Fixes dEQP-GLES3.functional.fbo.completeness.renderable.texture.color0.rgb5_a1
* st/va: Return correct width and height for encode/decode supportMark Thompson2017-10-171-10/+30
| | | | | | | | | | Previously this would return the largest possible buffer size, which is much larger than the codecs themselves support. This caused confusion when client applications attempted to decode 8K video thinking it was supported when it isn't. Signed-off-by: Mark Thompson <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: Fix config entrypoint handlingMark Thompson2017-10-171-6/+12
| | | | | | | | | Consistently use it as a PIPE_VIDEO_ENTRYPOINT. v2: Return an error if the entrypoint is not set (Christian). Signed-off-by: Mark Thompson <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: Disable vaExportSurfaceHandle()Mark Thompson2017-10-172-2/+2
| | | | | | | This is not in libva 2.0, so it shouldn't be enabled yet. Signed-off-by: Mark Thompson <[email protected]> Acked-by: Christian König <[email protected]>
* meson: build llvmpipeDylan Baker2017-10-163-1/+121
| | | | | Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: build softpipeDylan Baker2017-10-163-1/+94
| | | | | | | | | | This doesn't include llvmpipe. v2: - Fix inconsistent use of with_gallium_swrast and with_gallium_softpipe. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* meson: build nouveau (gallium) driverDylan Baker2017-10-164-1/+261
| | | | | | | | | | | Tested with a GK107. v2: - Add target for nouveau standalone compiler. This target is not built by default. v3: - Add nouveau to list of drivers built by default Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <eric at anholt.net>
* meson: build radeonsi gallium driverDylan Baker2017-10-163-3/+91
| | | | | | | | | | This hooks up the bits necessary to build gallium dri drivers, with radeonSI as the first example driver. This isn't tested yet. v4: - drop radeonsi generated header from sources. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <eric at anholt.net>
* meson: build gallium winsys for dri, null, and wrapperDylan Baker2017-10-166-7/+123
| | | | | Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <eric at anholt.net>
* meson: build radeonsiDylan Baker2017-10-165-0/+237
| | | | | | | | This builds the radeonsi (and radeon) window system bits and gallium driver bits. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <eric at anholt.net>
* meson: Build gallium dri state trackerDylan Baker2017-10-162-0/+58
| | | | | Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <eric at anholt.net>
* meson: build gallium helper driversDylan Baker2017-10-165-0/+116
| | | | | | | This builds ddebug, noop, rbug, and trace drivers. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <eric at anholt.net>
* meson: Build gallium pipe-loaderDylan Baker2017-10-163-0/+67
| | | | Signed-off-by: Dylan Baker <[email protected]>
* meson: Build gallium auxiliaryDylan Baker2017-10-162-0/+551
| | | | | | | v2: - guard gallivm files with "with_llvm" instead of "dep_llvm.found()" Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (v1)
* svga: format the version string like the rest of mesaEric Engestrom2017-10-161-5/+5
| | | | | | | | All 4 other version strings do it like this. ((Also, double parentheses just look confusing)) Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* svga: fix format_conversion_table breakageBrian Paul2017-10-161-2/+7
| | | | | | | | | | The new A1B5G5R5_UNORM, X1B5G5R5_UNORM formats were added in the wrong place in commit ef874ee450b18e. Fixes: ef874ee450b18e "gallium: Add support for 5551 with the 1-bit field in the low bit." Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* a2xx: add support for a few 16-bit color rendering formatsIlia Mirkin2017-10-152-1/+11
| | | | | | | | The rest should be possible too, just needs some additional investigation. Passes fbo-*-formats piglit tests. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]>
* freedreno/a20x: Enable rendering to RGBA/RGBXWladimir J. van der Laan2017-10-151-1/+3
| | | | | Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* freedreno/a20x: Fix rendering to BGRXWladimir J. van der Laan2017-10-151-0/+1
| | | | | | | Make sure that BGRX rendering is swapped the correct way around. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* etnaviv: rework TS enable to be a derived stateLucas Stach2017-10-143-5/+43
| | | | | | | | | | | | | | | Draw operations should not use the TS if the TS buffer content is invalid, as this leads to wrong rendering or even GPU hangs. As the TS valid status can change between draws (clear operations changing it to valid, blits using the RS to the color or ZS buffer changing it to invalid), the TS_MEM_CONFIG must be updated before each draw if the status has changed. This fixes the remaining TS related piglit failures (regressions of a standard run against a piglit run with TS completely disabled). Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: skip unused vertex attributes when assigning VS inputsLucas Stach2017-10-141-0/+4
| | | | | | | | | | | | | When not all of the vertex attributes are actually used in the shader, we end up with some inputs without an assigned reg. Those are marked as invalid and must be skipped when assigning the inputs, as those would overwrite other valid inputs otherwise. Fixes piglit drawpixels and a bunch of other tests using the st_draw path. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* st/dri: Add definitions to allow importing 16-bit surfacesMark Thompson2017-10-131-0/+14
| | | | | | | Necessary to support P010/P016 surfaces for video. Signed-off-by: Mark Thompson <[email protected]> Acked-by: Leo Liu <[email protected]>
* broadcom/vc5: Remove the u_resource_vtbl usage.Eric Anholt2017-10-123-25/+18
| | | | Like for vc4, this was just a wasted indirection.
* radeonsi: implement sync_file import/exportMarek Olšák2017-10-122-2/+79
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* winsys/amdgpu: implement sync_file import/exportMarek Olšák2017-10-123-7/+138
| | | | | | syncobj is used internally for interactions with command submission. Reviewed-by: Nicolai Hähnle <[email protected]>
* ac: add radeon_info::has_sync_filecros-mesa-17.2.3-vanillachadv/cros-mesa-17.2.3-vanillaMarek Olšák2017-10-121-0/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* st/dri: implement __DRIimageExtension::validateUsage properlyMarek Olšák2017-10-121-8/+22
| | | | | Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add pipe_screen::check_resource_capabilityMarek Olšák2017-10-125-0/+74
| | | | | | | | | This is optional (and no CAP). Implemented by radeonsi, ddebug, rbug, trace. Reviewed-by: Daniel Stone <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* etnaviv: Do GC3000 resolve-in-place when possibleWladimir J. van der Laan2017-10-124-4/+25
| | | | | | | | | | | | | If an RS blit is done with source exactly the same as destination, and the hardware supports this, do an in-place resolve. This only fills in tiles that have not been rendered to using information from the TS. This is the same as the blob does and potentially saves significant bandwidth when doing i.MX6qp scanout using PRE, and when rendering to textures (though here using sampler TS would be even better). Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
* radeonsi: add support for PIPE_FORMAT_{X1,A1}R5G5B5_UNORMNicolai Hähnle2017-10-121-0/+8
| | | | | | Fixes dEQP-EGL.functional.image.modify.tex_rgb5_a1_tex_subimage_rgba8 Reviewed-by: Marek Olšák <[email protected]>
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