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* tgsi: use tgsi_semantic enum type in ureg codeBrian Paul2018-02-072-23/+23
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* tgsi: use TGSI enum types in ureg codeBrian Paul2018-02-072-51/+55
| | | | | | v2: fix enum tgsi_interpolate_mode/loc typo. Reviewed-by: Roland Scheidegger <[email protected]>
* gallium/util: replace uint with tgsi enum typesBrian Paul2018-02-072-6/+7
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* gallium/util: replace unsigned with tgsi enum typesBrian Paul2018-02-072-31/+34
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* r600: fix rendering regression on r6/7 gpusDave Airlie2018-02-081-1/+6
| | | | | | | | Fixes: 2d5b5d267e (r600: work out target mask at framebuffer bind.) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104989 Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: avoid int-to-pointer-cast warnings on 32bitGrazvydas Ignotas2018-02-081-6/+12
| | | | | | | I hope the actual dropping of MSB is ok, but that's what's already happened before this change. Reviewed-by: Marek Olšák <[email protected]>
* gallium/hud: update some query functionsGrazvydas Ignotas2018-02-084-4/+4
| | | | | | | | It seems these were missed when struct pipe_context * argument was added to hud_graph::query_new_value. Fixes: 3132afdf4c "gallium/hud: pass pipe_context explicitly to most functions" Reviewed-by: Marek Olšák <[email protected]>
* Revert "gallium: build ddebug, noop, rbug, trace as part of auxiliary"Roland Scheidegger2018-02-0714-54/+98
| | | | | | This reverts commit 6f82b8d8d0a986aac28e7bec47fc313fb950475c. This broke scons build, and reportedly clover with autotools/meson too.
* gallium: build ddebug, noop, rbug, trace as part of auxiliaryMarek Olšák2018-02-0714-98/+54
| | | | | | | Building gallium is faster by 7.5 seconds on a 4core/8thread 3GHz CPU. (gallium build time is reduced by 15% when building only radeonsi) Non-recursive makefiles are great!
* u_blit: (trivial) fix bogus argument order for set_fragment_shaderRoland Scheidegger2018-02-071-2/+2
| | | | | Amazingly this still worked sometimes, albeit I'm not even sure why... This fixes d7bec6f7a6a2a35c80be939db8532011af1e9b67.
* u_blit,u_simple_shaders: add shader to convert from xrbias formatRoland Scheidegger2018-02-074-16/+78
| | | | | | | | | | | | | | | We need this to handle some oddball dx10 format (DXGI_FORMAT_R10G10B10_XR_BIAS_A2_UNORM). What you can do with this format is very limited, hence we don't want to add it as a gallium format (we could not express the properties of this format as ordinary format properties neither, so like all special formats it would need specific code for handling it in any case). While here, also nuke the array for different shaders for different writemasks, as it was not actually used (always full masks are passed in for generating shaders). Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* u_simple_shaders: fix mask handling in util_make_fragment_tex_shader_writemaskRoland Scheidegger2018-02-071-1/+1
| | | | | | | | | | | The writemask handling was busted, since writing defaults to output meant they got overwritten by the tex sampling anyway. Albeit the affected components were undefined, so maybe with some luck it still would have worked with some drivers - if not could as well kill it... (This would have affected u_blitter but not u_blit since the latter always used xyzw mask.) Reviewed-by: Brian Paul <[email protected]>
* radeonsi/nir: add nir support for compiling compute shadersTimothy Arceri2018-02-073-18/+39
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ac/radeonsi: add num_work_groups to the abiTimothy Arceri2018-02-072-3/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ac/radeonsi: create ac_build_shader_clock() helperTimothy Arceri2018-02-071-5/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ac/radeonsi: add load_local_group_size() to the abiTimothy Arceri2018-02-071-0/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add get_block_size() helperTimothy Arceri2018-02-071-20/+27
| | | | | | This will be reused by the nir backend in a later patch. Reviewed-by: Marek Olšák <[email protected]>
* ac/radeonsi: add local_invocation_ids to the abiTimothy Arceri2018-02-072-3/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* ac/radeonsi: add workgroup_ids to the abiTimothy Arceri2018-02-072-6/+4
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: gather some compute info in si_nir_scan_shader()Timothy Arceri2018-02-071-6/+27
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: always set input_usage_mask as using all componentsTimothy Arceri2018-02-071-4/+10
| | | | | | | | | | | This fixes a regression for now, in the future we should gather the used components properly. V2: just set for VS and correctly handle doubles Fixes: be973ed21f6e "radeonsi: load the right number of components for VS inputs and TBOs" Reviewed-by: Marek Olšák <[email protected]>
* r600: fixup sparse color exports.Dave Airlie2018-02-073-1/+12
| | | | | | | | | | | | | | | If we have gaps in the shader mask we have to have 0x1 in them according to a comment in radeonsi, and this is required to fix the test at least on cayman. We also need to record the highest one written to write to the ps exports reg. This fixes: KHR-GL45.enhanced_layouts.fragment_data_location_api Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: work out target mask at framebuffer bind.Dave Airlie2018-02-073-4/+9
| | | | | | | If we only get 1,2,3,6 framebuffers we want a sparse target mask. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: work out shader export mask at shader build time (v1.1)Dave Airlie2018-02-076-3/+13
| | | | | | | | | | | Since enhanced layouts allows setting specific MRT outputs, we can get sparse outputs, so we have to calculate the shader mask earlier. v1.1: update checks for state update (Roland) Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: fix xfb stream check.Dave Airlie2018-02-071-1/+1
| | | | | | | | | This fixes: KHR-GL45.enhanced_layouts.xfb_vertex_streams Reviewed-by: Roland Scheidegger <[email protected]> Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/compute: add render cond support.Dave Airlie2018-02-071-2/+5
| | | | | | | | | | Set render cond and emit atom. Fixes: KHR-GL45.compute_shader.conditional-dispatching Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: fix not-very indirect computeDave Airlie2018-02-071-12/+18
| | | | | | | | | | | | | We need to get the grid sizes earlier to fill in to the const buffer. Fixes: KHR-GL45.compute_shader.built-in-variables and KHR-GL45.compute_shader.dispatch-indirect Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: overhaul buffer resource query.Dave Airlie2018-02-071-7/+8
| | | | | | | | | | | | | This cleans up and fixes the previous fix even more. Buffers from textures start at max const, buffers from buffers/images come in from the 168 offset. This fixes a bunch of: KHR-GL45.shader_storage_buffer_object* Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/eg: fix buffer sizing.Dave Airlie2018-02-071-1/+3
| | | | | | | | | | | For buffers we want the size in bytes, For images we want it in elements. This fixes: KHR-GL45.shader_storage_buffer_object.advanced-unsizedArrayLength-cs-std430-vec-pad Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/images: set offset for compute shaders with number of declared samplersDave Airlie2018-02-071-1/+1
| | | | | | | | for frag shaders we get a value in the key, I expect I need to make compute work better Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/compute: only mark buffer/image state dirty for fragment shadersDave Airlie2018-02-071-2/+4
| | | | | | | | | | | The compute emission path always emits this currently, and emitting it on the fragment path breaks the blitter. This fixes gpu hangs in KHR-GL45.compute_shader.resource-texture Reviewed-by: Roland Scheidegger <[email protected]> Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/atomic: fix ATOMCAS instruction.Dave Airlie2018-02-071-1/+31
| | | | | | | | | | This has 4 srcs. This fixes: KHR-GL45.shader_atomic_counter_ops_tests.ShaderAtomicCounterOpsExchangeTestCase Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/sb/cayman: fix indirect ubo access on caymanDave Airlie2018-02-071-1/+1
| | | | | | | | | | | | | | With sb enabled on cayman, this was overwriting the proper cf index value with random ones if the dst gpr was 2 or 3, only save the value for a MOVA instruction. Fixes: KHR-GL45.gpu_shader5.uniform_blocks_array_indexing (on cayman with sb) Cc: <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/eg: use texture target to pick array size not view target (v2)Dave Airlie2018-02-071-7/+10
| | | | | | | | | | | | | | This fixes a few CTS cases in : KHR-GL45.texture_view.view_sampling some multisample cases are still broken, but not sure this is the same problem. v2: fix more cases Cc: <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* winsys/amdgpu: allow non page-aligned size bo creation from pointerMichal Navratil2018-02-061-4/+7
| | | | | | | | | Fix INVALID_OPERATION caused by BufferData with target EXTERNAL_VIRTUAL_MEMORY_BUFFER_AMD when the buffer size is not page aligned. Signed-off-by: Marek Olšák <[email protected]> Cc: 17.3 18.0 <[email protected]>
* meson: ensure xmlpool/options.h is generated for libgalliumJon Turney2018-02-061-1/+1
| | | | | | | | | | | In file included from ../src/gallium/targets/dri/target.c:1: In file included from ../src/gallium/auxiliary/target-helpers/drm_helper.h:8: ../src/util/xmlpool.h:103:10: fatal error: 'xmlpool/options.h' file not found See also 26bde1e3. Signed-off-by: Jon Turney <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* r600/fp64: Fix build.Vinson Lee2018-02-051-1/+1
| | | | | | | | | | | | | CC r600_shader.lo r600_shader.c: In function ‘egcm_int_to_double’: r600_shader.c:4543:12: error: ‘ctx’ is a pointer; did you mean to use ‘->’? if (ctx.bc->chip_class == CAYMAN) ^ -> Fixes: 35b430157776 ("r600/fp64: fix integer->double conversion") Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* r600/fp64: fix integer->double conversionDave Airlie2018-02-061-28/+93
| | | | | | | | | | | | | Doing a straight uint/int->fp32->fp64 conversion causes some precision issues, Roland suggested splitting the integer into two portions and doing two separate int->fp32->fp64 conversions then adding the results. This passes the tests in CTS and piglit. [airlied: fix cypress conversion opcodes] Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: enable vcn encode for HEVC mainBoyuan Zhang2018-02-051-1/+3
| | | | | | | Enable vcn encode for HEVC main profile on Raven. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* st/va: implement HEVC encode functionsBoyuan Zhang2018-02-051-6/+144
| | | | | | | Implement HEVC encode functions based on VAAPI HEVC encode interface. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* st/va: add HEVC encode functionsBoyuan Zhang2018-02-055-4/+111
| | | | | | | Add a separate file for HEVC encode functions. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* st/va: enable dual instances encode only for H264Boyuan Zhang2018-02-052-11/+15
| | | | | | | | Logics that related to dual instances encode should only be done for H264, not other codecs. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* st/va: add entrypoint check for HEVCBoyuan Zhang2018-02-051-10/+12
| | | | | | | Add entrypoint check for HEVC to differentiate decode and encode jobs. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* st/va: add HEVC picture descBoyuan Zhang2018-02-052-4/+23
| | | | | | | | Add HEVC picture desc, and add codec check when creating and destroying context. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* st/va: move H264 enc functions into separate fileBoyuan Zhang2018-02-055-139/+260
| | | | | | | | | Move all H264 encode related functions into separate file. Similar to VAAPI decode side, there will be separate file for each codec on encode side as well. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add header implementations for HEVCBoyuan Zhang2018-02-051-1/+347
| | | | | | | | Implement encoding of sps, pps, vps, aud, and slice headers for HEVC based on HEVC specs. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add ib implementations for HEVCBoyuan Zhang2018-02-051-45/+222
| | | | | | | Implement required ibs for vcn HEVC encode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: support picture parameters for HEVCBoyuan Zhang2018-02-053-21/+64
| | | | | | | | | Pass pipe_picture_desc instead of pipe_h264_enc_picture_desc so that it can be used for different codecs. Add functions to handle picture parameters that will be used for HEVC encode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* radeon/vcn: add vcn encode interface for HEVCBoyuan Zhang2018-02-051-2/+79
| | | | | | | | Add vcn encode interface for HEVC, and rename radeon_enc_h264_enc_pic to radeon_enc_pic since radeon_enc_pic is used by both H264 and HEVC. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
* vl: add parameters for HEVC encodeBoyuan Zhang2018-02-051-0/+99
| | | | | | | Add HEVC encode interface Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Christian König <[email protected]>
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