summaryrefslogtreecommitdiffstats
path: root/src/gallium
Commit message (Collapse)AuthorAgeFilesLines
* ilo: drop ptr from ilo_transferChia-I Wu2014-07-282-35/+36
| | | | | With the recent clean-ups, we can pass the mapped pointer around between functions cleanly. Drop it to make ilo_transfer smaller.
* ilo: s/TRANSFER_MAP_UNSYNC/TRANSFER_MAP_GTT_UNSYNC/Chia-I Wu2014-07-282-6/+6
| | | | | It maps to drm_intel_gem_bo_map_unsynchronized(), which results in unsynchronized GTT mapping.
* ilo: drop unused context param from transfer functionsChia-I Wu2014-07-281-115/+100
| | | | Many of the transfer functions do not need an ilo_context. Drop it.
* ilo: tidy up transfer mapping/unmappingChia-I Wu2014-07-281-88/+89
| | | | | | Add xfer_map() to replace map_bo_for_transfer(). Add xfer_unmap() and xfer_alloc_staging_sys() to simplify texture and buffer mapping/unmapping, and enable more code sharing between them.
* ilo: tidy up choose_transfer_method()Chia-I Wu2014-07-281-84/+164
| | | | | | Add a bunch of helper functions and a big comment for choose_transfer_method(). This also fixes handling of PIPE_TRANSFER_MAP_DIRECTLY to not ignore tiling.
* ilo: free transfers with util_slab_free()Chia-I Wu2014-07-281-1/+1
| | | | We used FREE() in one of the error path.
* clover: Add clUnloadPlatformCompiler.EdB2014-07-282-1/+6
| | | | Reviewed-by: Francisco Jerez <[email protected]>
* clover: Add clCreateProgramWithBuiltInKernels.EdB2014-07-282-1/+23
| | | | | | | [ Francisco Jerez: Check for devices not associated with the specified context. Style fix. ] Reviewed-by: Francisco Jerez <[email protected]>
* ilo: simplify ilo_flush()Chia-I Wu2014-07-263-20/+30
| | | | Move fence creation to the new ilo_fence_create().
* r600g/compute: Defrag the pool at the same time as we grow itBruno Jiménez2014-07-252-23/+19
| | | | | | | | | | | | This allows us two things: we now need less item copies when we have to defrag+grow the pool (to just one copy per item) and, even in the case where we don't need to defrag the pool, we reduce the data copied to just the useful data that the items use. Note: The fallback path is a bit ugly now, but hopefully we won't need it much. Reviewed-by: Tom Stellard <[email protected]>
* r600g/compute: Try to use a temporary resource when growing the poolBruno Jiménez2014-07-251-18/+43
| | | | | | | | | | | | | Now, before moving everything to host memory, we try to create a new resource to use as a pool. I we succeed we just use this resource and delete the previous one. If we fail we fallback to using the shadow. This should make growing the pool faster, and we can also save 64KB of memory that were allocated for the 'shadow', even if they weren't used. Reviewed-by: Tom Stellard <[email protected]>
* freedreno: fix typo in gpu version checkRob Clark2014-07-251-1/+1
| | | | | | | Opps, I should use larger fonts, I guess. Reported-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: split out shader compiler from a3xxRob Clark2014-07-2525-477/+580
| | | | | | | | | | | | | | | | | | | | | | Move the bits we want to share between generations from fd3_program to ir3_shader. So overall structure is: fdN_shader_stateobj -> ir3_shader -> ir3_shader_variant -> ir3 |- ... \- ir3_shader_variant -> ir3 So the ir3_shader becomes the topmost generation neutral object, which manages the set of variants each of which generates, compiles, and assembles it's own ir. There is a bit of additional renaming to s/fd3_compiler/ir3_compiler/, etc. Keep the split between the gallium level stateobj and the shader helper object because it might be a good idea to pre-compute some generation specific register values (ie. anything that is independent of linking). Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: rename ir3_shader to ir3Rob Clark2014-07-2512-55/+55
| | | | | | | | First step of reoganization split out compiler (so it can be shared between a3xx and a4xx). Rename ir3_shader -> ir3 (since we'll want the name ir3_shader for a higher level object). Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: scheduler vs pred regRob Clark2014-07-252-3/+51
| | | | | | | The scheduler also needs to be aware of predicate register (p0) in addition to address register (a0). Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: little cleanupsRob Clark2014-07-254-39/+19
| | | | | | Remove some obsolete comments, rename deref->addr. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: enable/disable wa's based on patch-levelRob Clark2014-07-254-8/+34
| | | | | | | | It seems like for the most part, different behaviors, workarounds, etc, should be conditional on GPU patch revision (ie. a320.0 vs a320.2) rather than GPU id (a320 vs a330). Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: make IR heap dyanmicRob Clark2014-07-252-8/+43
| | | | | | | | | | | | The fixed size heap is a remnant of the fdre-a3xx assembler. Yet it is convenient for being able to free the entire data structure in one shot without worrying about leaking nodes. Change it to dynamically grow the heap size (adding chunks) as needed so we don't have an artificial upper limit on shader size (other than hw limits) and don't always have to allocate worst-case size. Signed-off-by: Rob Clark <[email protected]>
* r600g/compute: Fix singed/unsigned comparison compiler warnings.Jan Vesely2014-07-251-7/+7
| | | | | | | The iteration variables go from 0 anyway. Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* clover: Query the device to see if images are supportedTom Stellard2014-07-253-1/+8
| | | | Reviewed-by: Francisco Jerez <[email protected]>
* gallium: Add PIPE_CAP_COMPUTE_IMAGES_SUPPORTEDTom Stellard2014-07-253-1/+11
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* r600g/compute: Allow compute_memory_defrag to defragment between resourcesBruno Jiménez2014-07-252-5/+7
| | | | | | This will be used in the following patch to avoid duplicated code Reviewed-by: Tom Stellard <[email protected]>
* r600g/compute: Allow compute_memory_move_item to move items between resourcesBruno Jiménez2014-07-252-16/+16
| | | | | | v2: Remove unnecesary variables Reviewed-by: Tom Stellard <[email protected]>
* winsys/radeon: fix indentationJerome Glisse2014-07-241-29/+29
| | | | | | | Can we please keep it clean and avoid ending up in messy situation like ddx. Signed-off-by: Jérôme Glisse <[email protected]>
* nvc0/ir: support 2d constbuf indexingIlia Mirkin2014-07-241-0/+14
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gm107/ir: emit LDC subopsIlia Mirkin2014-07-241-0/+1
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gk110/ir: emit load constant subopIlia Mirkin2014-07-241-0/+1
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: fix phi/union sources when their def has been mergedIlia Mirkin2014-07-241-0/+8
| | | | | | | | | | | | | In a situation where double-register values are used, the phi nodes can still end up being u32 values. They all get merged into one RA node though. When fixing up the merge (which comes after the phi node), the phi node's def would get fixed, but not its sources which would remain at the low register value. This maintains the invariant that a phi node's defs and sources are allocated the same register. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: fix hard-coded TYPE_U32 sized registerIlia Mirkin2014-07-241-3/+4
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: mark shader header if fp64 is usedIlia Mirkin2014-07-241-0/+2
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: keep track of whether the program uses fp64Ilia Mirkin2014-07-242-2/+7
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: make sure that the local memory allocation is aligned to 0x10Ilia Mirkin2014-07-241-1/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* ilo: check the tilings of imported handlesChia-I Wu2014-07-241-30/+36
| | | | Just to be cautious.
* ilo: clean up resource bo renamingChia-I Wu2014-07-244-51/+63
| | | | | s/alloc_bo/rename_bo/ as that is what the functions do. Simplify bo allocation and move the complexity to bo renaming.
* ilo: share some code between {tex,buf}_create_boChia-I Wu2014-07-241-59/+55
| | | | | Add resource_get_bo_name() and resource_get_bo_initial_domain() for use by both functions.
* ilo: use native 3-component vertex formats on GEN7.5+Chia-I Wu2014-07-242-1/+6
| | | | GEN7.5 gains support for those formats natively.
* ilo: allow for device-dependent format translationChia-I Wu2014-07-245-32/+39
| | | | Pass ilo_dev_info to all format translation functions.
* freedreno/a3xx/compiler: fix p0 (kill, etc)Rob Clark2014-07-231-1/+2
| | | | | | | Don't assert (debug builds) or assign random uninitialized value for predicate register (p0).. that screws up kill, etc. Signed-off-by: Rob Clark <[email protected]>
* Revert "r600g/compute: Fix warnings"Tom Stellard2014-07-232-16/+12
| | | | | | This reverts commit 467f1585e28adba0e94ef593de131bc327f098bb. This breaks the build on some systems.
* radeon/llvm: fix formattingGrigori Goronzy2014-07-231-10/+14
| | | | | | | Use K&R and same indent as most other code. No functional change intended. Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: enable unsafe math for graphics shadersGrigori Goronzy2014-07-231-0/+5
| | | | | | | | | | | Accuracy of some operations was recently improved in the R600 backend, at the cost of slower code. This is required for compute shaders, but not for graphics shaders. Add unsafe-fp-math hint to make LLVM generate faster but possibly less accurate code. Piglit didn't indicate any regressions. Reviewed-by: Tom Stellard <[email protected]>
* r600g/compute: Fix warningsTom Stellard2014-07-232-12/+16
|
* r600g: Use hardware sqrt instructionGlenn Kennard2014-07-232-7/+4
| | | | | | | Piglit quick tests including sqrt pass, no other regressions, tested on radeon 6670. Reviewed-by: Alex Deucher <[email protected]>
* r600g/compute: Remove unneeded code from compute_memory_promote_itemBruno Jiménez2014-07-232-36/+12
| | | | | | | | | | | | Now that we know that the pool is defragmented, we positively know that allocated + unallocated will be the total size of the current pool plus all the items that will be promoted. So we only need to grow the pool once. This will allow us to just add the new items to the end of the item_list without the need of looking for a place to the new item. Reviewed-by: Tom Stellard <[email protected]>
* r600g/compute: Quick exit if there's nothing to add to the poolBruno Jiménez2014-07-231-0/+4
| | | | | | | | This way we can avoid defragmenting the pool, even if it is needed to defragment it, and looping again through the list of unallocated items. Reviewed-by: Tom Stellard <[email protected]>
* r600g/compute: Defrag the pool if it's necesaryBruno Jiménez2014-07-232-17/+19
| | | | | | | | | | | | | | | | | This patch adds a new member to the pool to track its status. For now it is used only for the 'fragmented' status, but if needed it could be used for more statuses. The pool will be considered fragmented if: An item that isn't the last is freed or demoted. This 'strategy' has a problem, although it shouldn't cause any bug. If for example we have two items, A and B. We choose to free A first, now the pool will have the 'fragmented' status. If we now free B, the pool will retain its 'fragmented' status even if it isn't fragmented. Reviewed-by: Tom Stellard <[email protected]>
* r600g/compute: Add a function for defragmenting the poolBruno Jiménez2014-07-232-0/+28
| | | | | | | | | | | This new function will move items forward in the pool, so that there's no gap between them, effectively defragmenting the pool. For now this function is a bit dumb as it just moves items forward without trying to see if other items in the pool could fit in the gaps. Reviewed-by: Tom Stellard <[email protected]>
* r600g/compute: Add a function for moving items in the poolBruno Jiménez2014-07-232-0/+93
| | | | | | | | | | | | | | | | This function will be used in the future by compute_memory_defrag to move items forward in the pool. It does so by first checking for overlaping ranges, if the ranges don't overlap it will copy the contents directly. If they overlap it will try first to make a temporary buffer, if this buffer fails to allocate, it will finally fall back to a mapping. Note that it will only be needed to move items forward, it only checks for overlapping ranges in that case. If needed, it can easily be added by changing the first if. Reviewed-by: Tom Stellard <[email protected]>
* freedreno/a3xx: more vtx formatsRob Clark2014-07-231-0/+17
| | | | | | | | Actually what we currently handle is just the SCALED versions, and not the int versions. The difference probably matters more when we actually support integer in the compiler. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: const file relative addressingRob Clark2014-07-238-68/+203
| | | | | | | | | | | | | | | | | | Teach new compiler scheduling and register assignment how to deal with relative addressing. This gets us what we need to avoid falling back to old compiler for CONST[ADDR[0].x+n]. It is also a prerequisite for temp file relative addressing, although that is going to also need some cleverness in register assignment to keep arrays grouped together. NOTE: doing address calculation in full precision and then narrowing to s16 in the mov to addr reg seems to sometimes cause lockups (and sometimes work?!). It seems more reliable to do the address calculation in s16, like the blob does. Which means teaching RA how to deal with mixed half and full precision allocation. Fortunately that didn't turn out to be too hard, so that is a nice bonus which we could probably take better advantage of elsewhere. Signed-off-by: Rob Clark <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-21 13:42:17 +0000