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* freedreno: mark stencil buffer valid too in case of z32x24s8Rob Clark2017-12-042-2/+4
* freedreno: remove use of u_transferRob Clark2017-12-0411-41/+30
* freedreno: add -Wno-packed-bitfield-compat for meson buildEric Engestrom2017-12-041-2/+12
* nvc0/ir: Properly lower 64-bit shifts when the shift value is >32Pierre Moreau2017-12-041-1/+1
* st/glsl_to_nir/radeonsi: enable gs support for nir backendTimothy Arceri2017-12-042-29/+35
* ac: add si_nir_load_input_gs() to the abiTimothy Arceri2017-12-043-0/+30
* radeonsi: create si_llvm_load_input_gs()Timothy Arceri2017-12-042-23/+44
* radeonsi: pass llvm type to lds_load()Timothy Arceri2017-12-041-13/+13
* radeonsi: add llvm_type_is_64bit() helperTimothy Arceri2017-12-041-0/+9
* radeonsi: pass llvm type to si_llvm_emit_fetch_64bit()Timothy Arceri2017-12-043-12/+18
* radeonsi: add nir support for gs epilogueTimothy Arceri2017-12-041-4/+21
* radeonsi: add nir support for es epilogueTimothy Arceri2017-12-041-16/+13
* radeonsi: add nir support for ls epilogueTimothy Arceri2017-12-041-15/+14
* st/glsl_to_nir: enable NIR link time optsTimothy Arceri2017-12-041-7/+27
* radeonsi/nir: add support for packed inputsTimothy Arceri2017-12-041-21/+25
* freedreno/ir3: relax barriersRob Clark2017-12-031-2/+2
* freedreno/ir3: all mem instructions have WAR hazzardRob Clark2017-12-031-1/+1
* freedreno: add debug option to force emulated indirectRob Clark2017-12-033-0/+12
* freedreno: also mark draw-indirect buffer as readRob Clark2017-12-031-0/+7
* freedreno: small cleanupsRob Clark2017-12-031-17/+8
* freedreno: avoid unneccessary batch flushRob Clark2017-12-031-0/+2
* freedreno: avoid mem2gmem for invalidated buffersRob Clark2017-12-033-2/+17
* freedreno: deferred flush supportRob Clark2017-12-035-4/+32
* freedreno: rework fence trackingRob Clark2017-12-0312-61/+109
* freedreno: proper locking for iterating dependent batchesRob Clark2017-12-032-8/+20
* freedreno/a5xx: correct max_indicies for indirect drawsRob Clark2017-12-031-1/+2
* broadcom/vc4: Use a single-entry cached last_hindex value.Eric Anholt2017-12-012-2/+20
* broadcom/vc4: Decompose single QUADs to a TRIANGLE_FAN.Eric Anholt2017-12-011-5/+14
* broadcom/vc4: Skip emitting redundant VC4_PACKET_GEM_HANDLES.Eric Anholt2017-12-013-3/+12
* broadcom/vc4: Simplify the relocation handling for index buffers.Eric Anholt2017-12-012-17/+17
* broadcom/vc4: Fix handling of GFXH-515 workaround with a start vertex count.Eric Anholt2017-12-011-16/+27
* broadcom/vc4: Fix the scaling factor for the GFXH-515 workaround.Eric Anholt2017-12-011-1/+1
* meson: use dep_thread instead of dependency('threads') in freedrenoDylan Baker2017-12-011-1/+1
* meson: Add lmsensors supportDylan Baker2017-12-015-4/+7
* gallium/hud: use #ifdef to test for macro existenceEric Engestrom2017-12-016-11/+11
* amd: remove always-true BRAHMA_BUILD defineEric Engestrom2017-12-011-3/+1
* swr/scons: Fix intermittent build failureGeorge Kyriazis2017-12-011-0/+1
* r600: add ARB_shader_storage_buffer_object support (v3)Dave Airlie2017-12-016-22/+369
* r600/cayman: looks like cmpxchg moved to ZDave Airlie2017-12-011-2/+5
* r600/shader: fix 64->32 conversionsDave Airlie2017-12-011-35/+54
* radeonsi/gfx9: fix importing shared textures with DCCMarek Olšák2017-11-301-1/+1
* mesa: add AllowGLSLCrossStageInterpolationMismatch workaroundTapani Pälli2017-11-303-0/+4
* etnaviv: GC7000: Factor out state based texture functionalityWladimir J. van der Laan2017-11-308-308/+454
* etnaviv: GC7000: Move active_samplers_bits to textureWladimir J. van der Laan2017-11-303-12/+17
* etnaviv: GC7000: Factor out incompatible texture handling logicWladimir J. van der Laan2017-11-302-16/+31
* etnaviv: GC7000: Track dirty sampler viewsWladimir J. van der Laan2017-11-304-2/+10
* etnaviv: GC7000: Make point sprites work on HALTI5Wladimir J. van der Laan2017-11-303-6/+24
* etnaviv: GC7000: State changes for HALTI3..5Wladimir J. van der Laan2017-11-304-73/+218
* etnaviv: GC7000: Update screen specs for HALTI5Wladimir J. van der Laan2017-11-301-4/+15
* etnaviv: GC7000: Update context reset for ..HALTI5Wladimir J. van der Laan2017-11-301-5/+32