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* r600g: make sure copying of all texture formats is acceleratedMarek Olšák2012-08-042-52/+54
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* gallium/u_blitter: add a query for checking whether copying is supportedMarek Olšák2012-08-044-37/+77
| | | | v2: add comments
* r600g: don't decompress depth or stencil if there isn't anyMarek Olšák2012-08-044-9/+17
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* r600g: correct texture memory size for Z32F_S8X24 on evergreenMarek Olšák2012-08-041-7/+16
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* gallium/u_blitter: remove fallback for stencil copy that all drivers skippedMarek Olšák2012-08-044-15/+5
| | | | Reviewed-by: Brian Paul <[email protected]>
* gallium/u_blitter: add ability to blit only depth or only stencilMarek Olšák2012-08-043-14/+17
| | | | Reviewed-by: Brian Paul <[email protected]>
* gallium: define PIPE_MASK_RGBAZSMarek Olšák2012-08-041-0/+1
| | | | | | I need this and it seems like it could be useful. Reviewed-by: Brian Paul <[email protected]>
* gallium/u_blitter: minor cleanupMarek Olšák2012-08-042-8/+8
| | | | Reviewed-by: Brian Paul <[email protected]>
* gallium/tgsi: fixup texture name stringsMarek Olšák2012-08-041-4/+4
| | | | Reviewed-by: Brian Paul <[email protected]>
* gallium/u_blitter: set sample mask to ~0Marek Olšák2012-08-042-0/+20
| | | | Reviewed-by: Brian Paul <[email protected]>
* gallium/u_blit: bail out if src is a multisample textureMarek Olšák2012-08-041-0/+6
| | | | Reviewed-by: Brian Paul <[email protected]>
* gallium/u_blit: check nr_samples before using resource_copy_regionMarek Olšák2012-08-041-1/+2
| | | | Reviewed-by: Brian Paul <[email protected]>
* gallium: set sample mask to ~0 for clear, blit and gen_mipmapMarek Olšák2012-08-044-1/+23
| | | | | | | The sample mask affects single-sampled rendering too (it's orthogonal to the color mask). Reviewed-by: Brian Paul <[email protected]>
* r600g: fix F2U opcode translationDave Airlie2012-08-041-1/+1
| | | | Signed-off-by: Marek Olšák <[email protected]>
* draw: Ensure channel in convert_to_soa is initialized.Vinson Lee2012-08-031-1/+1
| | | | | | | Fixes uninitialized pointer read defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* u_blitter: Move a pointer dereference after null check.Vinson Lee2012-08-031-2/+3
| | | | | | | Fixes dereference before null check defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* Use C99 NAN and INFINITY macrosMatt Turner2012-08-031-10/+3
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* gallium/tests/trivial: updates for CSO interface changesBrian Paul2012-08-031-2/+2
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* st/xorg: updates for CSO interface changesBrian Paul2012-08-032-7/+9
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* st/xa: updates for CSO interface changesBrian Paul2012-08-034-9/+9
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* vega: fix build breakage from cso sampler/view changesBrian Paul2012-08-031-17/+17
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* cso: remove unreachable break statementsBrian Paul2012-08-031-5/+0
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* cso: 80-column wrapping, remove trailing whitespace, etcBrian Paul2012-08-031-33/+54
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* gallium: consolidate CSO sampler and sampler_view functionsBrian Paul2012-08-037-254/+150
| | | | | | | | | | | | | Merge the vertex/fragment versions of the cso_set/save/restore_samplers() functions. Now we pass the shader stage (PIPE_SHADER_x) to the function to indicate vertex/fragment/geometry samplers. For example: cso_single_sampler(cso, PIPE_SHADER_FRAGMENT, unit, sampler); This results in quite a bit of code reduction, fewer CSO functions and support for geometry shaders. Reviewed-by: Marek Olšák <[email protected]>
* radeon/llvm: Add $(LLVM_LDFLAGS) to the loader linker flagsTom Stellard2012-08-021-1/+1
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* radeon/llvm: Add support for more f32 CMP instructions on SITom Stellard2012-08-021-5/+15
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* radeon/llvm: Add support for fneg on SITom Stellard2012-08-022-0/+16
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* radeon/llvm: Add support for fp_to_sint on SITom Stellard2012-08-021-1/+3
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* radeon/llvm: Remove CMOVLOG DAG nodeTom Stellard2012-08-026-75/+9
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* radeonsi: Properly initialize si_shader_ctx.radeon_bldTom Stellard2012-08-021-0/+1
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* radeonsi: Handle TGSI TXP opcode.Michel Dänzer2012-08-021-2/+24
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: Handle TGSI DIV opcode.Michel Dänzer2012-08-021-0/+5
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* svga: remove questionable INLINE qualifiersBrian Paul2012-08-021-2/+2
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* svga: sort #includesBrian Paul2012-08-021-4/+4
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* svga: add some comments in svga_screen_cache.cBrian Paul2012-08-021-1/+14
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* svga: whitespace, formatting fixesBrian Paul2012-08-021-52/+54
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* svga: remove unneeded 'struct svga_screen' declarationsBrian Paul2012-08-022-2/+0
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* radeonsi: initial VDPAU targetChristian König2012-08-022-0/+54
| | | | | | | | Windowed speed is of course way to slow, but fullscreen works like a charm now. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeon/llvm: fix fp immediates on SIChristian König2012-08-021-7/+20
| | | | | | | | I don't know if this is a good idea, but it fixes the problem at hand. Signed-off-by: Christian König <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeonsi: fix TEX writemaskChristian König2012-08-021-2/+2
| | | | | | | | | Using the writemask in the sampler results in packet VGPRS. For now just sample all components and let llvm chose the right one. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix shader param and color countChristian König2012-08-021-5/+6
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: fix texture loads from sampler > 0Christian König2012-08-021-2/+2
| | | | | | | | | The backend is multiplying the offset by the numbers of elements anyway, so doing it twice just makes everything crash. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: disable tiling until we fixed all bugsChristian König2012-08-021-0/+2
| | | | | | | Currently there are more important things to worry about. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* scons: Add support for Intel Compiler.Vinson Lee2012-08-011-1/+1
| | | | | | | The patch makes the SCons build with Intel Compiler successful. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* nv50,nvc0: make resolve sampler objects allow sRGB conversionChristoph Bumiller2012-08-013-12/+25
| | | | | | | Just figured out what that bit does. Note: It's converted back to sRGB on write, so no effective conversion occurs.
* Revert "gallium: specify resource_resolve destination via a pipe_surface"Christoph Bumiller2012-08-015-33/+49
| | | | | | | | | | | This reverts commit 5d5af7d359e0060fa00b90a8f04900b96f9058b0. It turns out the issue this was supposed to fix merely counter-acted a bug in the hardware driver that I wasn't aware of. The resource_resolve is not supposed to do sRGB conversion, period. (This would violate the requirement that source and destination must be of the same format).
* radeon/llvm: fix calculation of max register numberChristian König2012-08-011-1/+1
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Add pseudo-support for 64-bit immediate types on SITom Stellard2012-07-312-0/+23
| | | | | | | | SI does not support 64-bit immediates natively, but llvm will generate i64 immediates when indexing loads and stores (since SI has 64-bit pointers). The i64 indices will always be small enough to fit into 32-bits (i.e. the high 32 bits will always be all zeros), so we can treat these index values as 32-bits.
* radeon/llvm: Fix incorrect return value in SelectADDRReg()Tom Stellard2012-07-311-1/+1
| | | | We need to return true when we match the pattern.
* radeon/llvm: Move SMRD IMM pattern before SMRD SGPR patternTom Stellard2012-07-311-7/+6
| | | | | | | In tablegen, if two patterns match, the one that comes first in the file is given preference. We want the SMRD IMM pattern to be given preference, because it encodes the pointer offset in its immediate field, which saves us an add instruction.
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