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* gallium/radeon: remove DBG_TEXMIPMarek Olšák2015-12-033-4/+2
| | | | | | we don't need 2 flags for dumping texture info Reviewed-by: Michel Dänzer <[email protected]>
* gallium/aux/util: Trivial, we already have format use itEdward O'Callaghan2015-12-031-1/+1
| | | | | | | No need to dereference again, fixup for clarity. Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* automake: Fix typo in MSVC2008 compat flags.Jose Fonseca2015-12-031-1/+1
| | | | | | | | | It should be MSVC2008_COMPAT_CFLAGS and not MSVC2008_COMPAT_CXXFLAGS. This is why the recent util_blitter breakage went unnoticed on autotools builds. Trivial.
* ttn: Whitelist from -Werror=declaration-after-statement.Jose Fonseca2015-12-031-0/+4
| | | | | | | | | nir is the exception among gallium/auxiliary -- we don't need to compile it with MSVC2008 yet. And this enables us to use -Werror=declaration-after-statement in the next commit as we should, without complicated fixes to tgsi_to_nir module. Trvial. Tested with GCC and Clang.
* st/wgl: add new stw_ext_rendertexture.c fileBrian Paul2015-12-031-0/+252
| | | | | | This should have been included in the previous commit. Signed-off-by: Brian Paul <[email protected]>
* st/wgl: add support for WGL_ARB_render_textureBrian Paul2015-12-039-10/+118
| | | | | | | | | | | There are a few legacy OpenGL apps on Windows which need this extension. We basically use glCopyTex[Sub]Image to implement wglBindTexImageARB (see the implementation notes for details). v2: refactor code to use st_copy_framebuffer_to_texture() helper function. Reviewed-by: José Fonseca <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* nv50/ir: fix moves to/from flagsIlia Mirkin2015-12-022-2/+7
| | | | | | | | Noticed this when looking at a trace that caused flags to spill to/from registers. The flags source/destination wasn't encoded correctly according to both envydis and nvdisasm. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: don't forget to mark flagsDef on cvt in txb loweringIlia Mirkin2015-12-021-1/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nv50/ir: fix instruction permutation logicIlia Mirkin2015-12-021-1/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nv50/ir: the mad source might not have a defining instructionIlia Mirkin2015-12-021-1/+1
| | | | | | | For example if it's $r63 (aka 0), there won't be a definition. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nv50/ir: make sure entire graph is reachableIlia Mirkin2015-12-021-0/+1
| | | | | | | | The algorithm expects the entire CFG to be reachable, so make sure that we hit every node. Otherwise we will end up with uninitialized data, memory corruption, etc. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: deal with loops with no breaksIlia Mirkin2015-12-021-0/+6
| | | | | | | | | | | For example if there are only returns, the break bb will not end up part of the CFG. However there will have been a prebreak already emitted for it, and when hitting the RET that comes after, we will try to insert the current (i.e. break) BB into the graph even though it will be unreachable. This makes the SSA code sad. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nvc0/ir: fold postfactor into immediateIlia Mirkin2015-12-021-0/+6
| | | | | | | | SM20-SM50 can't emit a post-factor in the presence of a long immediate. Make sure to fold it in. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* nv50/ir: allow immediate 0 to be loaded anywhereIlia Mirkin2015-12-021-0/+6
| | | | | | | There's a post-RA fixup to replace 0's with $r63 (or $r127 if too many regs are used), so just as nvc0, let an immediate 0 be loaded anywhere. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir/gk110: add memory barriers support for GK110Samuel Pitoiset2015-12-021-0/+12
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nv50/ir: do not call textureMask() for surface opsSamuel Pitoiset2015-12-021-1/+2
| | | | | | | | | | | That texture mask thing doesn't seem to be needed for surface ops, so just as nve4+, let do that only for texture ops. This fixes a segfault with 'test_surface_st' from gallium/tests/trivial/compute.c on Fermi because this test uses sustp. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* util/blitter: Fix "SO C90 forbids mixed declarations and code".Jose Fonseca2015-12-021-2/+4
| | | | Trivial.
* gallium/util: Fix util_blitter_clear_depth_stencil() for num_layers>1Edward O'Callaghan2015-12-021-4/+12
| | | | | | | | | Previously util_blitter_clear_depth_stencil() could not clear more than the first layer. We need to generalise this as we did for util_blitter_clear_render_target(). Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* gallium/util: Fix util_blitter_clear_render_target() for num_layers>1Edward O'Callaghan2015-12-021-3/+12
| | | | | | | | | Previously util_blitter_clear_render_target() could not clear more than the first layer. We need to generalise this so that ARB_clear_texture can pass the 3d piglit test. Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* Remove Sun CC specific code.Jose Fonseca2015-12-023-14/+6
| | | | | Reviewed-by: Matt Turner <[email protected]> Acked-by: Alan Coopersmith <[email protected]>
* r600: set mega fetch count to 16 for gs copy shaderDave Airlie2015-12-021-0/+1
| | | | | | Seems like MFC should be set for this shader. Signed-off-by: Dave Airlie <[email protected]>
* r600: increment ring index after emit vertex not before.Dave Airlie2015-12-021-18/+24
| | | | | | | The docs say we should send the emit after the ring writes, so lets do that and not have an ALU in between. Signed-off-by: Dave Airlie <[email protected]>
* r600: add alu + cf nop to copy shader on r600Dave Airlie2015-12-021-0/+10
| | | | | | | SB suggests we do this for r600, so lets do it, for the copy shader. Signed-off-by: Dave Airlie <[email protected]>
* r600: SMX returns CONTEXT_DONE early workaroundDave Airlie2015-12-022-1/+13
| | | | | | | | | streamout, gs rings bug on certain r600s, requires a wait idle before each surface sync. Reviewed-by: Marek Olšák <[email protected]> Cc: "10.6 11.0 11.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: do SQ flush ES ring rolling workaroundDave Airlie2015-12-023-1/+8
| | | | | | | | | Need to insert a SQ_NON_EVENT when ever geometry shaders are enabled. Reviewed-by: Marek Olšák <[email protected]> Cc: "10.6 11.0 11.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nv50,nvc0: allow to create resources other than buffersSamuel Pitoiset2015-12-015-4/+9
| | | | | | | | | | | | For the compute support, we might stick buffers as surfaces. This fixes an assertion when executing src/gallium/tests/trivial/compute. To avoid using these "restricted" surfaces as render targets, these assertions have been moved. Note that it's already handled for the framebuffer thing on nvc0. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* clover: Handle NULL devices returned by pipe_loader_probe() v2Tom Stellard2015-12-011-1/+2
| | | | | | | | | | | | | | | | | | | | | When probing for devices, clover will call pipe_loader_probe() twice. The first time to retrieve the number of devices, and then second time to retrieve the device structures. We currently assume that the return value of both calls will be the same, but this will not be the case if a device happens to disappear between the two calls. When a device disappears, the pipe_loader_probe() will add a NULL device to the device list, so we need to handle this. v2: - Keep range for loop Reviewed-by: Francisco Jerez <[email protected]> Acked-by: Emil Velikov <[email protected]> CC: <[email protected]>
* automake: fix some occurrences of hardcoded -ldl and -lpthreadJonathan Gray2015-12-011-1/+1
| | | | | | | | | Correct some occurrences of -ldl and -lpthread to use $(DLOPEN_LIBS) and $(PTHREAD_LIBS) respectively. Signed-off-by: Jonathan Gray <[email protected]> Cc: "11.0 11.1" <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* st/va: also retrieve reference frames info for h264Julien Isorce2015-12-011-0/+52
| | | | | | | | Other hardwares than AMD require to parse: VAPictureParameterBufferH264.ReferenceFrames[16] Signed-off-by: Julien Isorce <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: delay decoder creation until max_references is knownJulien Isorce2015-12-014-34/+68
| | | | | | | | | | | | | | | | | | In general max_references cannot be based on num_render_targets. This patch allows to allocate buffers with an accurate size. I.e. no more than necessary. For other codecs it is a fixed value 2. This is similar behaviour as vaapi/vdpau-driver. For now HEVC case defaults to num_render_targets as before. But it could also benefits this change by setting a more accurate max_references number in handlePictureParameterBuffer. Signed-off-by: Julien Isorce <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* r600: workaround empty geom shader.Dave Airlie2015-12-011-0/+5
| | | | | | | | | | We need to emit at least one cut/emit in every geometry shader, the easiest workaround it to stick a single CUT at the top of each geom shader. Reviewed-by: Marek Olšák <[email protected]> Cc: "10.6 11.0 11.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: rv670 use at least 16es/gs threadsDave Airlie2015-12-011-4/+5
| | | | | | | | This is specified in the docs for rv670 to work properly. Reviewed-by: Marek Olšák <[email protected]> Cc: "10.6 11.0 11.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: geometry shader gsvs itemsize workaroundDave Airlie2015-12-011-0/+20
| | | | | | | | | | On some chips the GSVS itemsize needs to be aligned to a cacheline size. This only applies to some of the r600 family chips. Reviewed-by: Marek Olšák <[email protected]> Cc: "10.6 11.0 11.1" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/shader: split address get out to a function.Dave Airlie2015-12-011-1/+6
| | | | | | | This will be used in the tess shaders. Reviewed-by: Oded Gabbay <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* vl/buffers: fixes vl_video_buffer_formats for RGBXJulien Isorce2015-11-301-1/+1
| | | | | | | Fixes: 42a5e143a8d "vl/buffers: add RGBX and BGRX to the supported formats" Cc: [email protected] Signed-off-by: Julien Isorce <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* r600: move per-type settings into a switch statementDave Airlie2015-11-301-5/+13
| | | | | | | This will allow adding tess stuff much cleaner later. Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: split out common alu_writes pattern.Dave Airlie2015-11-301-7/+12
| | | | | | | | This just splits out a common pattern into an inline function to make things cleaner to read. Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/llvm: fix r600/llvm buildDave Airlie2015-11-301-1/+1
| | | | | | Reported on irc by gryffus Signed-off-by: Dave Airlie <[email protected]>
* r600: fixes for register definitions.Dave Airlie2015-11-301-3/+3
| | | | | | Forgot to add these. Signed-off-by: Dave Airlie <[email protected]>
* r600: add missing register to initial stateDave Airlie2015-11-303-7/+15
| | | | | | | | | | We really should initialise HS/LS_2 and SQ_LDS_ALLOC exists on all evergreen not just cayman, so we should initialise it as well. Reviewed-by: Glenn Kennard <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: define registers required for tessellationDave Airlie2015-11-302-27/+113
| | | | | | | | | This adds the defines for a bunch of registers and shader values that are required to implement tessellation. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: consolidate clip state updatesDave Airlie2015-11-302-17/+16
| | | | | | | | Move some common code into one place, tess will also need to use this function. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nv50/ir: always display the opcode number for unknown instructionsSamuel Pitoiset2015-11-292-2/+2
| | | | | | | This helps in debugging unknown instructions. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* auxiliary/vl/dri: fd management cleanupsEmil Velikov2015-11-291-2/+5
| | | | | | | | | | Analogous to previous commit, minus the extra dup. We are the one opening the device thus we can directly use the fd. Spotted by Coverity (CID 1339867, 1339877) Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]>
* auxiliary/vl/drm: fd management cleanupsEmil Velikov2015-11-291-1/+7
| | | | | | | | | Analogous to previous commit. Spotted by Coverity (CID 1339868) Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]>
* st/xa: fd management cleanupsEmil Velikov2015-11-291-1/+8
| | | | | | | | | Analogous to previous commit. Spotted by Coverity (CID 1339866) Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]>
* st/dri: fd management cleanupsEmil Velikov2015-11-291-2/+14
| | | | | | | | | | | Add some checks if the original/dup'd fd is valid and ensure that we don't leak it on error. The former is implicitly handled within the pipe_loader, although let's make things explicit and check beforehand. Spotted by Coverity (CID 1339865) Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]>
* pipe-loader: check if winsys.name is non-null prior to strcmpEmil Velikov2015-11-291-4/+4
| | | | | | | | | | | | In theory this wouldn't be an issue, as we'll find the correct name and break out of the loop before we hit the sentinel. Let's fix this and avoid issues in the future. Spotted by Coverity (CID 1339869, 1339870, 1339871) Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]>
* st/va: add missing break statementEmil Velikov2015-11-291-0/+1
| | | | | | | | | | | | | | Earlier commit factored out the mpeg4 IQ matrix handling into separate function, although it forgot to add a break in its case statement. Thus the data ended up partially overwritten as the mpeg4 and h265 structs are members of the desc union. Spotted by Coverity (CID 1341052) Fixes: 64761a841db "st/va: move MPEG4 functions into separate file" Cc: Julien Isorce <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon: only suspend queries on flush if they haven't been suspended yetNicolai Hähnle2015-11-282-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Non-timer queries are suspended during blits. When the blits end, the queries are resumed, but this resume operation itself might run out of CS space and trigger a flush. When this happens, we must prevent a duplicate suspend during preflush suspend, and we must also prevent a duplicate resume when the CS flush returns back to the original resume operation. This fixes a regression that was introduced by: commit 8a125afa6e88a3eeddba8c7fdc1a75c9b99d5489 Author: Nicolai Hähnle <[email protected]> Date: Wed Nov 18 18:40:22 2015 +0100 radeon: ensure that timing/profiling queries are suspended on flush The queries_suspended_for_flush flag is redundant because suspended queries are not removed from their respective linked list. Reviewed-by: Marek Olšák <[email protected]> Reported-by: Axel Davy <[email protected]> Cc: "11.1" <[email protected]> Tested-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
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