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* util/u_endian: set PIPE_ARCH_*_ENDIAN to 1Dylan Baker2019-11-0525-69/+56
| | | | | | | | | | | | This will allow it to be used as a drop in replacement for _mesa_little_endian in a number of cases. v2: - Always define PIPE_ARCH_LITTLE_ENDIAN and PIPE_ARCH_BIG_ENDIAN, define the one that reflects the host system to 1 and the other to 0 - replace all uses of #ifdef, #ifndef, and #if defined() with #if and #if ! with PIPE_ARCH_*_ENDIAN Reviewed-by: Eric Engestrom <[email protected]>
* svga: check return value of define_query_vgpu{9,10}Philipp Sieweck2019-11-051-8/+23
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* nir: pack nir_variable::data::streamMarek Olšák2019-11-041-2/+2
| | | | Reviewed-by: Connor Abbott <[email protected]>
* iris: try to set the specified tiling when importing a dmabufJames Xiong2019-11-043-11/+29
| | | | | | | | | | | | | | | | | | When importing a dmabuf with a specified tiling, the dmabuf user should always try to set the tiling mode because: 1) the exporter can set tiling AFTER exporting/importing. 2) a dmabuf could be exported from a kernel driver other than i915, in this case the dmabuf user and exporter need to set tiling separately. This patch fixes a problem when running vkmark under weston with iris on ICL, it crashed to console with the following assert. i965 doesn't have this problem as it always tries to set the specified tiling mode. weston: ../src/gallium/drivers/iris/iris_resource.c:990: iris_resource_from_handle: Assertion `res->bo->tiling_mode == isl_tiling_to_i915_tiling(res->surf.tiling)' failed. Signed-off-by: James Xiong <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* iris: Fix "Force Zero RTA Index Enable" setting againKenneth Graunke2019-11-041-1/+1
| | | | | | | | | | In 2ca0d913ea8, we began updating cso_fb->layers to the actual layer count, rather than 0. This fixed cases where we were setting "Force Zero RTA Index Enable" even when doing layered rendering. Sadly, it also broke the check entirely: cso_fb->layers is now 1 for non-layered cases, but the Force Zero RTA Index check was still comparing for 0. Fixes: 2ca0d913ea8 ("iris: Fix framebuffer layer count")
* panfrost: MALI_DEPTH_TEST is actually MALI_DEPTH_WRITEMASKBoris Brezillon2019-11-041-1/+2
| | | | | | | | | MALI_DEPTH_TEST should only be set when depth->writemask is true, not when the depth test is enabled. Let's rename the flag and patch panfrost_bind_depth_stencil_state() to do the right thing. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* nv50/ir: fix crash in isUniform for undefined valuesKarol Herbst2019-11-031-0/+2
| | | | | Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* lima: set dithering flag when necessaryVasily Khoruzhick2019-11-011-1/+3
| | | | | | | Bit 13 in aux1 enables dithering Reviewed-by: Qiang.Yu <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima: ignore flags while looking for BO in cacheVasily Khoruzhick2019-11-011-2/+2
| | | | | | | | | Any BO would work, we don't have any BO types yet anyway. Moreover lima_submit_add_bo() changes BO flags so they won't match allocation flags. Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima: align size before trying to fetch BO from cacheVasily Khoruzhick2019-11-011-2/+2
| | | | | | | Otherwise we may be looking in wrong bucket Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* lima: add debug prints for BO cacheVasily Khoruzhick2019-11-013-6/+56
| | | | | | | | LIMA_DEBUG=bocache now activates debug prints for BO allocation, destruction and BO cache. Reviewed-by: Erico Nunes <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* pan/midgard: Use fp32 blend shadersAlyssa Rosenzweig2019-11-012-10/+10
| | | | | | | | | Clearly we do want to have fp16 at some point ... but I kind of give up debugging and it turns out the issues with fp16 support in 'frost are so deeply rooted that I might as well disable this non-opt and land LCRA now. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* lima: support indexed draw with biasIcenowy Zheng2019-10-311-1/+1
| | | | | | | | | | | When doing an indexed draw with index_bias set to a non-zero value (e.g. by glDrawElementsBaseVertex), the vertex buffer should be offseted by index_bias vertices. Add this offset when setting the vertex buffer address. Signed-off-by: Icenowy Zheng <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]>
* zink: emit line-width when using polygon line-modeErik Faye-Lund2019-10-311-1/+20
| | | | | | | | When switching this to dynamic state, I forgot that this also needs to be emitted when we use a polygon-mode set to lines. Signed-off-by: Erik Faye-Lund <[email protected]> Fixes: 6d30abb4f14 ("zink: use dynamic state for line-width")
* targets/xvmc: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Dylan Baker <[email protected]>
* targets/xa: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Dylan Baker <[email protected]>
* targets/vdpau: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Dylan Baker <[email protected]>
* targets/va: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Dylan Baker <[email protected]>
* targets/omx: replace xmlpool_options_h with idep_xmlconfig_headersEric Engestrom2019-10-311-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Dylan Baker <[email protected]>
* pipe-loader: drop unnecessary xmlpool_options_hEric Engestrom2019-10-311-2/+2
| | | | | | | idep_xmlconfig already covers that Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Dylan Baker <[email protected]>
* pipe-loader: Build kmsro loader for with all kmsro targetsAlyssa Rosenzweig2019-10-311-1/+10
| | | | | | | | | | | | | | | Build failure reported by i965 CI, triggered by building dynamic pipeloaders with kmsro drivers (besides 'frost). At this point, there's no reason to actually do that -- mesa CI didn't mind -- but let's not break the build. v2: Simplify script. Add extra dependencies for v3d. Fixes: afb0d08cb0f ("pipe-loader: Default to kmsro if probe fails") Signed-off-by: Alyssa Rosenzweig <[email protected]> Reported-by: Clayton Craft <[email protected]> Tested-by: Clayton Craft <[email protected]> Reviewed-by: Tomeu Vizoso <[email protected]>
* zink: heap-allocate samplers objectsErik Faye-Lund2019-10-311-7/+14
| | | | | | | | | | VkSampler is 64-bit even on 32-bit systems, so casting it to a pointer is a bad idea there. So let's heap-allocate the sampler-object instead. Signed-off-by: Erik Faye-Lund <[email protected]> Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2017 Reviewed-by: Witold Baryluk <[email protected]> Tested-by: Witold Baryluk <[email protected]>
* radeonsi: tell the shader disk cache what IR is usedPierre-Eric Pelloux-Prayer2019-10-311-7/+10
| | | | | | | | | | | | | | | Until 8bef4df196fbb the IR (TGSI or NIR) was used in disk_cache driver_flags. This commit restores this features to avoid crashing when switching from one IR to the other. As radeonsi's default is TGSI, I used "driver_flags & 0x8000000 = 0" for TGSI to keep the same driver_flags. Fixes: 8bef4df196f ("radeonsi: add si_debug_options for convenient adding/removing of options") Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* android: Add panfrost support to build scriptsRobert Foss2019-10-314-1/+103
| | | | | | | | | | | | Currently the Android build system doesn't expose the panfrost driver. This patch enables the panfrost driver to be build on for the Android platform. Signed-off-by: Robert Foss <[email protected]> Reviewed-By: Rohan Garg <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* v3d: rename vertex shader key (num)_fs_inputs fieldsIago Toral Quiroga2019-10-311-13/+13
| | | | | | | | | | | | Until now this made sense because we always paired vertex shaders with fragment shaders, but as soon as we implement geometry and tessellation shaders that will no longer be the case, so rename this to (num_)used_outputs. v2: Use 'used_outputs' instead of ns_outputs, which is more explicit (Eric). Reviewed-by: Alejandro Piñeiro <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gallium/swr: Fix depth values for blit scenarioJan Zielinski2019-10-311-0/+8
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* iris/gen11+: Move flush for render target changeJordan Justen2019-10-311-19/+20
| | | | | | | | | | | | | | When starting a BLORP operation, we do the BTI-change flush. However, when ending it and transitioning back to regular drawing, we change the render target again - without a set_framebuffer_state() call. We need to do the BTI flush there too. BLORP flags IRIS_DIRTY_RENDER_BUFFER now, which will cause the next draw to get the BTI flush again. (explanation of fix by Ken) Fixes: 2b956a093a1 ("iris: totally untested icelake support") Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* iris: Add IRIS_DIRTY_RENDER_BUFFER state flagJordan Justen2019-10-311-1/+3
| | | | | | Fixes: 2b956a093a1 ("iris: totally untested icelake support") Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* lima: add cubemap supportArno Messiaen2019-10-316-8/+45
| | | | | | Signed-off-by: Arno Messiaen <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Reviewed-by: Erico Nunes <[email protected]>
* lima: introduce ppir_op_load_coords_reg to differentiate between loading ↵Arno Messiaen2019-10-316-5/+18
| | | | | | | | texture coordinates straight from a varying vs loading them from a register Signed-off-by: Arno Messiaen <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Reviewed-by: Erico Nunes <[email protected]>
* lima: add layer_stride field to lima_resource structArno Messiaen2019-10-313-15/+28
| | | | | | Signed-off-by: Arno Messiaen <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Reviewed-by: Erico Nunes <[email protected]>
* lima: fix stride in texture descriptorArno Messiaen2019-10-312-3/+3
| | | | | | Signed-off-by: Arno Messiaen <[email protected]> Reviewed-by: Vasily Khoruzhick <[email protected]> Reviewed-by: Erico Nunes <[email protected]>
* nv50/ir: mark STORE destination inputs as usedIlia Mirkin2019-10-301-0/+6
| | | | | | | | | | Observed an issue when looking at the code generatedy by the image-vertex-attrib-input-output piglit test. Even though the test itself worked fine (due to TIC 0 being used for the image), this needs to be fixed. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
* gm107/ir: fix loading z offset for layered 3d image bindingsIlia Mirkin2019-10-304-54/+202
| | | | | | | | | | | | | | | | | | | | | | | | Unfortuantely we don't know if a particular load is a real 2d image (as would be a cube face or 2d array element), or a layer of a 3d image. Since we pass in the TIC reference, the instruction's type has to match what's in the TIC (experimentally). In order to properly support bindless images, this also can't be done by looking at the current bindings and generating appropriate code. As a result all plain 2d loads are converted into a pair of 2d/3d loads, with appropriate predicates to ensure only one of those actually executes, and the values are all merged in. This goes somewhat against the current flow, so for GM107 we do the OOB handling directly in the surface processing logic. Perhaps the other gens should do something similar, but that is left to another change. This fixes dEQP tests like image_load_store.3d.*_single_layer and GL-CTS tests like shader_image_load_store.non-layered_binding without breaking anything else. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "20.0" <[email protected]>
* iris: Add Tile Cache Flush for Unified Cache.Rafael Antognolli2019-10-302-0/+21
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* etnaviv: fix non-pointsprite points on GC7000LJonathan Marek2019-10-301-0/+4
| | | | | | | | | | | | | Fixes these deqp tests (and more): dEQP-GLES2.functional.draw.draw_arrays.points.single_attribute dEQP-GLES2.functional.draw.draw_arrays.points.multiple_attributes dEQP-GLES2.functional.draw.draw_arrays.points.default_attribute dEQP-GLES2.functional.draw.draw_elements.points.single_attribute dEQP-GLES2.functional.draw.draw_elements.points.multiple_attributes dEQP-GLES2.functional.draw.draw_elements.points.default_attribute Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: stencil fixJonathan Marek2019-10-301-13/+15
| | | | | | | | | | | | | | | The final version of previous stencil fix patch ended up breaking one-sided stencil. Fixes remaining failures in these deqp tests (tested on GC3000/GC7000L): dEQP-GLES2.functional.fragment_ops.depth_stencil.* Note: deqp tests require --deqp-gl-config-name=rgba8888d24s8ms0 Fixes: 05da025f ("etnaviv: fix two-sided stencil") Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: fix depth biasJonathan Marek2019-10-302-1/+2
| | | | | | | | | | Fixes remaining failures in these deqp tests (tested on GC3000/GC7000L): dEQP-GLES2.functional.polygon_offset.* Fixes: 6c3c05dc ("etnaviv: fix polygon offset") Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* iris: Set MOCS for external surfaces to uncachedJordan Justen2019-10-301-4/+8
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* iris: Align fast clear color state buffer to a page.Rafael Antognolli2019-10-301-0/+5
| | | | | | | | | | | | | | | On gen11 and older, compressed images are tiled and aligned to 4K. On gen12 this 4K alignment restriction was removed. However, only aligning the fast clear color buffer to 64B (a cacheline, as it's on the documentation) is causing some bugs where the fast clear color is not converted during the fast clear operation. Aligning things to 4K seems to fix it. v2: Fix typo case in the comment (Nanley) v3: Rebase and fix conflicts. v4: Fix rebase mistake (Nanley). Reviewed-by: Nanley Chery <[email protected]>
* zink: only enable KHR_external_memory_fd if supportedErik Faye-Lund2019-10-303-7/+28
| | | | | | | | While we're at it, make sure we error out if it's not supported when required. This brings us a bit closer to being able to test on SwiftShader, which doesn't currently support KHR_external_memory_fd.
* freedreno/a2xx: add missing vertex formats (SSCALE/USCALE/FIXED)Jonathan Marek2019-10-307-49/+82
| | | | | | | | Mostly for vertex formats, but they are supported as texture formats too (untested however). Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* radeonsi: disable sdma for gfx10Pierre-Eric Pelloux-Prayer2019-10-301-1/+7
| | | | | | | | | | Disable sdma on gfx10 until all timeouts bugs are fixed. See: https://gitlab.freedesktop.org/mesa/mesa/issues/1907 https://bugs.freedesktop.org/show_bug.cgi?id=111481 Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: sdma misc fixesPierre-Eric Pelloux-Prayer2019-10-302-4/+2
| | | | | | SDMA IB doesn't need to be padded for SDMA. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: align sdma byte count to dwPierre-Eric Pelloux-Prayer2019-10-301-1/+12
| | | | | | | | | If src/dst addresses are dw aligned and size is > 4 then we align byte count to dw as well. PAL implementation works like this. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: enable 8K video decode support for HEVC and VP9Leo Liu2019-10-301-2/+18
| | | | | | | HW 8K decode support starts at Renoir Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Boyuan Zhang <[email protected]>
* radeon/vcn: Add VP9 8K decode supportLeo Liu2019-10-301-1/+1
| | | | | | | Require increase of context buffer size Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Boyuan Zhang <[email protected]>
* zink: drop nop descriptor-updatesErik Faye-Lund2019-10-301-4/+5
| | | | | | | If there's nothing to be done, let's actually do nothing. Seems like a good idea. Reviewed-by: Dave Airlie <[email protected]>
* zink: use bitfield for dirty flaggingErik Faye-Lund2019-10-302-7/+6
| | | | | | | Bitfields are a bit more ideomatic than explicit flags, and harder to get wrong. Reviewed-by: Dave Airlie <[email protected]>
* zink: use dynamic state for line-widthErik Faye-Lund2019-10-305-13/+17
| | | | | | | This will lead to fewer pipelines in the cache, which is assumed to become our most unavoidable performance bottle-neck down the line. Reviewed-by: Dave Airlie <[email protected]>
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