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* gallium: Remove unnecessary semicolonsEdward O'Callaghan2016-01-068-8/+9
* llvmpipe: Optimize lp_rast_triangle_32_3_16 for POWER8Oded Gabbay2016-01-061-1/+141
* llvmpipe: Optimize BUILD_MASK(_LINEAR) for POWER8Oded Gabbay2016-01-061-40/+110
* llvmpipe: Optimize do_triangle_ccw for POWER8Oded Gabbay2016-01-061-0/+100
* llvmpipe: add POWER8 portability file - u_pwr8.hOded Gabbay2016-01-061-0/+310
* draw: minor indentation fixBrian Paul2016-01-051-1/+1
* util: add debug_dump_ubyte_rgba_bmp()Brian Paul2016-01-052-0/+63
* svga: fix test for SVGA_NEW_STIPPLEBrian Paul2016-01-052-4/+8
* svga: add some comments in svga_state_vs.cBrian Paul2016-01-051-0/+3
* svga: change svga_hw_view_state::dirty to booleanBrian Paul2016-01-051-1/+1
* svga: avoid emitting redundant SetVertexBuffers() commandsBrian Paul2016-01-052-5/+26
* svga: check for no-ops in svga_bind_sampler_states()Brian Paul2016-01-051-1/+15
* build: enable st/va with nouveau driverJulien Isorce2016-01-051-0/+2
* nvc0: add support for st/vaJulien Isorce2016-01-053-50/+133
* nouveau: split nouveau_vp3_bsp in begin/next/endJulien Isorce2016-01-054-41/+77
* st/va: count number of slicesJulien Isorce2016-01-055-0/+25
* nvc0: scale up inter_bo size so that it's 16M for a 4K videoIlia Mirkin2016-01-041-2/+5
* nv50,nvc0: fix crash when increasing bsp bo size for h264Ilia Mirkin2016-01-042-4/+4
* radeonsi: remove unused parameter from si_shader_binary_read_configMarek Olšák2016-01-033-10/+7
* radeonsi: move si_shader_binary_upload out of si_shader_binary_readMarek Olšák2016-01-033-11/+10
* gallium/radeon: dump LLVM module outside of radeon_llvm_compileMarek Olšák2016-01-034-9/+12
* gallium/radeon: always add +DumpCode to the LLVM target machine for LLVM <= 3.5Marek Olšák2016-01-034-6/+5
* gallium/radeon: r600_can_dump_shader should get TGSI processor type directlyMarek Olšák2016-01-034-15/+10
* radeonsi: pass TGSI processor type to si_shader_binary_read for dumpingMarek Olšák2016-01-033-4/+5
* radeonsi: pass TGSI processor type to si_compile_llvm for dumpingMarek Olšák2016-01-033-5/+5
* radeonsi: rename shader parameter definitions and variables for more clarityMarek Olšák2016-01-033-43/+43
* nvc0/ir: add support for PK2H/UP2HIlia Mirkin2016-01-034-2/+28
* gallium: add PIPE_CAP_TGSI_PACK_HALF_FLOAT to indicate UP2H/PK2H supportIlia Mirkin2016-01-0316-0/+17
* tgsi: update PK2H/UP2H channel behavior infoIlia Mirkin2016-01-031-8/+8
* gallium: document PK2H/UP2HIlia Mirkin2016-01-031-2/+14
* freedreno/ir3: use NIR_PASS helper macrosRob Clark2016-01-031-19/+28
* freedreno/ir3: we require block_index metadataRob Clark2016-01-031-0/+2
* freedreno/ir3: refactor NIR IR handlingRob Clark2016-01-037-111/+202
* freedreno/ir3: drop unnecessary unreachable() caseRob Clark2016-01-031-2/+0
* gallium/tests: fix build with clang compilerSamuel Pitoiset2016-01-031-273/+330
* nv50,nvc0: optimize coherent buffer checking at draw timeSamuel Pitoiset2016-01-036-68/+82
* vc4: Fix build from upload changes.Eric Anholt2016-01-021-1/+1
* gallium/radeon: send LLVM diagnostics as debug messagesNicolai Hähnle2016-01-021-15/+46
* gallium/radeon: pass pipe_debug_callback into radeon_llvm_compile (v2)Nicolai Hähnle2016-01-027-9/+18
* radeonsi: send shader info as debug messages in addition to stderr outputNicolai Hähnle2016-01-021-14/+55
* radeonsi: pass pipe_debug_callback down into si_shader_binary_read (v2)Nicolai Hähnle2016-01-024-14/+22
* gallium/radeon: implement set_debug_callbackNicolai Hähnle2016-01-022-0/+14
* u_upload_mgr: allow specifying PIPE_USAGE_* for the upload bufferMarek Olšák2016-01-0216-23/+37
* u_upload_mgr: remove alignment parameter from u_upload_createMarek Olšák2016-01-0216-23/+15
* u_upload_mgr: pass alignment to u_upload_buffer manuallyMarek Olšák2016-01-023-2/+4
* u_upload_mgr: pass alignment to u_upload_data manuallyMarek Olšák2016-01-0216-19/+29
* u_upload_mgr: pass alignment to u_upload_alloc manuallyMarek Olšák2016-01-0221-23/+32
* u_upload_mgr: rework the application of alignmentMarek Olšák2016-01-021-10/+14
* nv50,nvc0: make sure there's pushbuf space and that we ref the bo earlyIlia Mirkin2016-01-014-6/+5
* nvc0: Set winding order regardless of domain.Kenneth Graunke2015-12-301-2/+4
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