summaryrefslogtreecommitdiffstats
path: root/src/gallium
Commit message (Expand)AuthorAgeFilesLines
* radeonsi: don't set VGT_LS_HS_CONFIG if it doesn't changeMarek Olšák2018-06-133-6/+12
* radeonsi: move VGT_GS_OUT_PRIM_TYPE into si_shader_gsMarek Olšák2018-06-134-33/+26
* radeonsi: record CLIPVERTEX output usage properly for compatibility profilesMarek Olšák2018-06-131-1/+0
* radeonsi: fix FBFETCH with 2D MSAA arraysMarek Olšák2018-06-131-1/+2
* radeonsi: return real memory usage instead of per-process usageMarek Olšák2018-06-131-2/+2
* virgl: add ARB_tessellation_shader support. (v2)Dave Airlie2018-06-147-8/+107
* freedreno/ir3: use pipe_image_view's cppRob Clark2018-06-111-1/+6
* freedreno/ir3: fix image dimensions offsetRob Clark2018-06-111-1/+1
* freedreno/a5xx: correct image/ssbo offsetRob Clark2018-06-111-1/+1
* freedreno/ir3: use saml always if we have lodRob Clark2018-06-111-1/+1
* freedreno/ir3: don't cp absneg into meta:fiRob Clark2018-06-111-0/+4
* freedreno/ir3: rework size/type conversion instructionsRob Clark2018-06-111-10/+156
* freedreno/ir3: propagate HALF flag across fanoutRob Clark2018-06-111-1/+4
* freedreno/a5xx: add sample-id/sample-mask-inRob Clark2018-06-111-3/+12
* freedreno/ir3: add sample-id/sample-mask-inRob Clark2018-06-111-0/+21
* freedreno: update generated headersRob Clark2018-06-118-87/+213
* freedreno/ir3: image atomics use image-store pathRob Clark2018-06-111-0/+8
* virgl: enable ARB_gpu_shader_fp64Dave Airlie2018-06-111-1/+2
* radeonsi: emit_dpbb_state packets optimizationSonny Jiang2018-06-072-21/+26
* radeonsi: emit_clip_state packets optimizationSonny Jiang2018-06-072-3/+7
* radeonsi: emit_msaa_sample_locs packets optimizationSonny Jiang2018-06-072-2/+6
* radeonsi: emit_msaa_config packets optimizationSonny Jiang2018-06-072-28/+28
* radeonsi: emit_cb_render_state packets optimizationSonny Jiang2018-06-073-9/+48
* radeonsi: emit_db_render_state packets optimizationSonny Jiang2018-06-075-29/+95
* drisw: Fix invalid pointer arithmeticJan Vesely2018-06-071-1/+1
* radeonsi: fix possible truncation on renderer stringTimothy Arceri2018-06-081-1/+1
* v3d: Work around GFXH-1461/GFXH-1689 by using CLEAR_TILE_BUFFERS.Eric Anholt2018-06-061-10/+17
* egl: rewire the build systems to use libwayland-eglEric Engestrom2018-06-061-1/+1
* r300g/swtcl: make pipe_context uploaders use malloc'd memory as beforeMarek Olšák2018-06-051-3/+6
* v3d: Be more explicit about include directory from our generated code.Eric Anholt2018-06-052-1/+4
* autotools: add missing android file to packageEric Engestrom2018-06-051-0/+1
* virgl: use bits in caps set v2[email protected]2018-06-052-0/+6
* virgl: add shader offset alignment to to v2 caps struct[email protected]2018-06-053-1/+4
* trace: Fix parsing of recent traces.Jose Fonseca2018-06-041-5/+26
* trace: Fix trace_context_transfer_unmap methods.Jose Fonseca2018-06-041-18/+42
* virgl: Always assume that ORIGIN_UPPER_LEFT and PIXEL_CENTER* are supportedGert Wollny2018-06-011-1/+2
* radeonsi: Fix crash on shaders using MSAA image load/storeAlex Smith2018-06-011-1/+7
* v3d: Fix automake linking error.Vinson Lee2018-05-301-1/+3
* virgl: Update virgl_hw.hJakob Bornecrantz2018-05-301-0/+1
* virgl: add ARB_transform_feedback_overflow_query supportDave Airlie2018-05-302-2/+4
* virgl: add polygon offset clampDave Airlie2018-05-301-1/+2
* virgl: add derivative control supportDave Airlie2018-05-301-1/+2
* virgl: add ARB_conditional_render_inverted supportDave Airlie2018-05-301-1/+2
* virgl: update caps bitset to latest version.Dave Airlie2018-05-301-0/+5
* nv30: add a couple of missed shader capsIlia Mirkin2018-05-301-0/+2
* nv30: ensure that displayable formats are marked accordinglyIlia Mirkin2018-05-301-4/+6
* gallium: add PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITYMarek Olšák2018-05-2918-0/+37
* drisw: use getImageShm() if availableMarc-André Lureau2018-05-301-1/+22
* drisw: learn to query shmid handle typeMarc-André Lureau2018-05-304-3/+12
* drisw: use shared memory when possibleMarc-André Lureau2018-05-301-12/+60
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-18 13:08:29 +0000