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* amd/common: add ac_vgt_gs_mode() helperSamuel Pitoiset2017-12-181-29/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* amd/common: add ac_get_cb_shader_mask() helperSamuel Pitoiset2017-12-181-33/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* r600: export robust buffer accessDave Airlie2017-12-181-1/+1
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600: export GLSL 430Dave Airlie2017-12-181-1/+1
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600/cs: add compute support to capsDave Airlie2017-12-181-2/+2
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600: always flush between gfx and computeDave Airlie2017-12-185-0/+21
| | | | | | | | This is in no way optimal, but there seems to be some problems mixing at the moment, lots of hangs, it is possible, just need to figure out more magic. Signed-off-by: Dave Airlie <[email protected]>
* r600: fix unused variable warningDave Airlie2017-12-181-1/+0
| | | | Signed-off-by: Dave Airlie <[email protected]>
* freedreno/a5xx: add a5xx blitterRob Clark2017-12-178-1/+498
| | | | | | FD_MESA_DEBUG=noblit to disable Signed-off-by: Rob Clark <[email protected]>
* freedreno: add generic blitterRob Clark2017-12-177-2/+161
| | | | | | | Basically a clone of util_blitter_blit() but with special handling to blit PIPE_BUFFER as a PIPE_TEXTURE_1D. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add non-draw batches for compute/blitRob Clark2017-12-1712-32/+82
| | | | | | | | | Get rid of "gmem" (ie. tiling) ringbuffer, and just emit setup commands directly to "draw" ringbuffer for compute (and in future for blits not using the 3d pipe). This way we can have a simple flat cmdstream buffer and bypass setup related to 3d pipe. Signed-off-by: Rob Clark <[email protected]>
* freedreno: track staging and shadow perf ctrs for the HUDRob Clark2017-12-175-0/+16
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: staging upload transfersRob Clark2017-12-173-43/+135
| | | | | | | | | | In the busy && !needs_flush case, we can support a DISCARD_RANGE upload using a staging buffer. This is a bit different from the case of mid- batch uploads which require us to shadow the whole resource (because later draws in an earlier tile happen before earlier draws in a later tile). Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-12-177-63/+334
| | | | Signed-off-by: Rob Clark <[email protected]>
* radeonsi: don't call force_dcc_off for buffersMarek Olšák2017-12-161-1/+1
| | | | | | | | This was undefined yet harmless behavior in LLVM. Not anymore - it causes a hang now. Cc: 17.3 <[email protected]> Tested-by: Michel Dänzer <[email protected]>
* radeon/uvd: add and manage render picture listBoyuan Zhang2017-12-151-4/+25
| | | | | | | | | | | | | | | | Create a list in decoder to store all render picture buffer pointers that currently being used in reference picture lists. During get message buffer call, check each pointer in render_pic_list[] within given pic->ref[] list, remove pointer that no longer being used by pic->ref[]. Then add current render surface pointer to the render_pic_list[] and assign the associated index to result.curr_idx. As a result, result.curr_idx will have the correct index to represent the current render picture, instead of the previous increamenting values. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vcn: add and manage render picture listBoyuan Zhang2017-12-151-4/+24
| | | | | | | | | | | | | | | | Create a list in decoder to store all render picture buffer pointers that currently being used in reference picture lists. During get message buffer call, check each pointer in render_pic_list[] within given pic->ref[] list, remove pointer that no longer being used by pic->ref[]. Then add current render surface pointer to the render_pic_list[] and assign the associated index to result.curr_idx. As a result, result.curr_idx will have the correct index to represent the current render picture, instead of the previous increamenting values. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* vl: remove is idr flagBoyuan Zhang2017-12-151-1/+0
| | | | | | | Remove is_idr flag since not being used anymore. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: directly use idr pic flagBoyuan Zhang2017-12-151-5/+3
| | | | | | | Remove is_idr flag, and use idr_pic_flag provided by vaapi directly Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: determine idr by pic typeBoyuan Zhang2017-12-151-1/+1
| | | | | | | | | Vaapi encode interface provides idr frame flags, where omx interface doesn't. Therefore, change to use picture type to determine idr frame, which will work for both interfaces. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: determine idr by pic typeBoyuan Zhang2017-12-151-1/+1
| | | | | | | | | | Vaapi encode interface provides idr frame flags, where omx interface doesn't. Therefore, change to use picture type to determine idr frame, which will work for both interfaces. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* swr/rast: Move more RTAI handling out of binnerTim Rowley2017-12-152-12/+2
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: EXTRACT2 changed from vextract/vinsert to vshuffleTim Rowley2017-12-153-61/+32
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Fix cache of API thread event managerTim Rowley2017-12-151-1/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Replace VPSRL with LSHRTim Rowley2017-12-154-41/+4
| | | | | | | | Replace use of x86 intrinsic with general llvm IR instruction. Generates the same final assembly. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Rework thread binding parameters for machine partitioningTim Rowley2017-12-157-88/+322
| | | | | | | | | | | | | Add BASE_NUMA_NODE, BASE_CORE, BASE_THREAD parameters to SwrCreateContext. Add optional SWR_API_THREADING_INFO parameter to SwrCreateContext to control reservation of API threads. Add SwrBindApiThread() function to allow binding of API threads to reserved HW threads. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Pull of RTAI gather & offset out of clip/bin codeTim Rowley2017-12-157-146/+203
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Remove no-op VBROADCAST of vIDTim Rowley2017-12-151-2/+2
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 Fetch - Fully widen 32-bit integer vertex componentsTim Rowley2017-12-154-17/+109
| | | | | | Also widen the 16-bit a 8-bit integer vertex component gathers to SIMD16. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Replace INSERT2 vextract/vinsert with JOIN2 vshuffleTim Rowley2017-12-153-105/+30
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 Fetch - Fully widen 16-bit float vertex componentsTim Rowley2017-12-151-7/+48
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 Fetch - Fully widen 32-bit float vertex componentsTim Rowley2017-12-154-32/+194
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Pass prim to ClipSimdTim Rowley2017-12-151-5/+5
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Pull most of the VPAI manipulation out of the binner/clipperTim Rowley2017-12-157-158/+177
| | | | | | Move out of binner/clipper; hand them down from the frontend code instead. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Move GatherScissors to headerTim Rowley2017-12-152-127/+127
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Rewrite Shuffle8bpcGatherd using shuffleTim Rowley2017-12-151-182/+62
| | | | | | Ease future code maintenance, prepare for folding simd8 and simd16 versions. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Convert gather masks to Nx1bitTim Rowley2017-12-152-40/+14
| | | | | | | Simplifies calling code, gets gather function interface closer to llvm's masked_gather. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: WIP - Widen fetch shader to SIMD16Tim Rowley2017-12-151-27/+689
| | | | | | Widen vertex gather/storage to SIMD16 for all component types. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Corrections to multi-scissor handlingTim Rowley2017-12-151-88/+88
| | | | | | | binner's GatherScissors() will be turned into a real gather in the not too distant future. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Binner fixes for viewport index offset handlingTim Rowley2017-12-152-2/+12
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Remove unneeded copy of gather maskTim Rowley2017-12-152-79/+23
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* freedreno: use u_transfer_helperRob Clark2017-12-152-229/+44
| | | | Signed-off-by: Rob Clark <[email protected]>
* gallium/util: add u_transfer_helperRob Clark2017-12-155-1/+649
| | | | | | | | | | | | | | | | | | | | | | | | Add a new helper that drivers can use to emulate various things that need special handling in particular in transfer_map: 1) z32_s8x24.. gl/gallium treats this as a single buffer with depth and stencil interleaved but hardware frequently treats this as separate z32 and s8 buffers. Special pack/unpack handling is needed in transfer_map/unmap to pack/unpack the exposed buffer 2) fake RGTC.. GPUs designed with GLES in mind, but which can other- wise do GL3, if native RGTC is not supported it can be emulated by converting to uncompressed internally, but needs pack/unpack in transfer_map/unmap 3) MSAA resolves in the transfer_map() case v2: add MSAA resolve based on Eric's "gallium: Add helpers for MSAA resolves in pipe_transfer_map()/unmap()." patch; avoid wrapping pipe_resource, to make it possible for drivers to use both this and threaded_context. Signed-off-by: Rob Clark <[email protected]>
* gallivm: implement accurate corner behavior for textureGather with cube mapsRoland Scheidegger2017-12-141-103/+201
| | | | | | | | | | | | | | | | The spec says the missing texel (when we wrap around both x and y axis) should be synthesized as the average of the 3 other texels. For bilinear filtering however we instead adjusted the filter weights (because, while the complexity looks similar, there would be 4 times as many color values to fix up than weights). Obviously this could not work for gather (hence accurate corner filtering was disabled with gather). Implement this by just doing it as the spec implies - calculate the 4th texel as the average of the other 3. With gather of course there's only one color to worry about, so it's not all that many instructions neither (albeit surely the whole cube map filtering is hilariously complex). Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: fix an issue with NaNs with seamless cube filteringRoland Scheidegger2017-12-141-0/+11
| | | | | | | | | | | | | | | | | | | Cube texture wrapping is a bit special since the values (post face projection) always are within [0,1], so we took advantage of that and omitted some clamps. However, we can still get NaNs (either because the coords already had NaNs, or the face projection generated them), and in fact we didn't handle them quite safely. I've seen -INT_MAX + 1 been propagated through as the final int coord value, albeit I didn't observe a crash. (Not quite a coincidence, since any stride mul with -INT_MAX or -INT_MAX+1 will turn up as a small positive number - nevertheless, I'd rather not try my luck, I'm not entirely sure it can't really turn up negative neither due to seamless coord swapping, plus ifloor of a NaN is not guaranteed to return -INT_MAX by any standard. And we kill off NaNs similarly with ordinary texture wrapping too.) So kill off the NaNs by using the common max against zero method. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* amd/common: add ac_build_waitcnt()Samuel Pitoiset2017-12-143-15/+4
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: make use of ac_build_fdiv()Samuel Pitoiset2017-12-141-7/+1
| | | | | | | And move the comment to amd/common. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: make use of ac_get_spi_shader_z_format()Samuel Pitoiset2017-12-143-23/+4
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* swr: Correct texture allocation and limit max size to 2GBBruce Cherniak2017-12-132-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes piglit tex3d-maxsize by correcting 4 things: The total_size calculation was using 32-bit math, therefore a >4GB allocation request overflowed and was not returning false (unsupported). Changed AlignedMalloc arguments from "unsigned int" to size_t, to handle >4GB allocations. Added error checking on texture allocations to fail gracefully. Finally, temporarily decreased supported max texture size from 4GB to 2GB. The gallivm texture-sampler needs some additional work to correctly handle larger than 2GB textures (offsets to LLVMBuildGEP are signed). I'm working on a follow-on patch to allow up to 4GB textures, as this is useful in HPC visualization applications. Fixes piglit tex3d-maxsize. v2: Updated patch description to clarify ">4GB". Reviewed-By: George Kyriazis <[email protected]>
* swr: Fix KNOB_MAX_WORKER_THREADS thread creation override.Bruce Cherniak2017-12-131-2/+1
| | | | | | | | | | | | | Environment variable KNOB_MAX_WORKER_THREADS allows the user to override default thread creation and thread binding. Previous commit to adjust linux cpu topology caused setting this KNOB to bind all threads to a single core. This patch restores correct functionality of override. Cc: <[email protected]> Reviewed-by: Tim Rowley <[email protected]>
* gallium/docs: document behavior of set_sample_mask()Brian Paul2017-12-131-1/+4
| | | | | | | | The sample mask is used even if msaa is not explicity enabled when we have a framebuffer with multisampled surfaces. That's DX behavior and what the Radeon drivers do. Not sure about other drivers at this point. Reviewed-by: Roland Scheidegger <[email protected]>
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