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* gallium: move ddebug, noop, rbug, trace to auxiliary to improve build timesMarek Olšák2018-04-1378-382/+96
* radeonsi: make sure CP DMA is idle at the end of IBsMarek Olšák2018-04-133-2/+16
* gallium/hud: add a simple HUD view that only draws textMarek Olšák2018-04-132-15/+60
* radeonsi: always prefetch later shaders after the draw packetMarek Olšák2018-04-133-26/+75
* radeonsi: emit shader pointers before cache flushes & waitsMarek Olšák2018-04-131-13/+7
* radeonsi/gfx9: don't use the workaround for gather4 + stencilMarek Olšák2018-04-131-2/+11
* radeonsi: disable TC-compat HTILE on Tonga and IcelandMarek Olšák2018-04-131-0/+7
* radeonsi: force 2D tiling on VI only when TC-compat HTILE is really enabledMarek Olšák2018-04-131-9/+7
* radeonsi: don't flush HTILE if there is no HTILE clearMarek Olšák2018-04-131-2/+2
* radeonsi: merge 2 identical if statements in si_clearMarek Olšák2018-04-131-9/+2
* radeonsi: don't do GFX-specific texture decompression for computeMarek Olšák2018-04-131-10/+10
* radeonsi: simplify generating the renderer stringMarek Olšák2018-04-131-11/+8
* Fix scons buildMarek Olšák2018-04-124-1/+10
* mesa: include mtypes.h lessMarek Olšák2018-04-122-2/+1
* broadcom/vc5: Fix a stray '`' in a comment.Eric Anholt2018-04-121-1/+1
* broadcom/vc5: Update the UABI for in/out syncobjsEric Anholt2018-04-129-90/+55
* broadcom/vc5: Drop the finished_seqno optimization.Eric Anholt2018-04-122-11/+0
* broadcom/vc5: Drop the throttling code.Eric Anholt2018-04-121-9/+0
* broadcom/vc5: Move flush_last_load into load_general, like for stores.Eric Anholt2018-04-121-28/+29
* broadcom/vc5: Rename read_but_not_cleared to loads_pending.Eric Anholt2018-04-121-13/+13
* broadcom/vc5: Refactor the implicit coords/stores_pending logic.Eric Anholt2018-04-121-23/+13
* broadcom/vc5: Emit missing TILE_COORDINATES_IMPLICIT in separate z/s stores.Eric Anholt2018-04-121-5/+16
* broadcom/vc5: Add checks that we don't try to do raw Z+S load/stores.Eric Anholt2018-04-121-0/+8
* broadcom/vc5: Fix MSAA depth/stencil size setup.Eric Anholt2018-04-121-2/+4
* st/va: add VP9 config to enable profile2Leo Liu2018-04-122-1/+5
* radeonsi: use PIPE_FORMAT_P016 format for VP9 profile2Leo Liu2018-04-121-1/+2
* radeon/vcn: add VP9 profile2 supportLeo Liu2018-04-121-0/+16
* vl: add VP9 profile2 supportLeo Liu2018-04-122-1/+3
* st/va: add VP9 config to enable profile0Leo Liu2018-04-122-1/+5
* st/va: parse VP9 uncompressed frame headerLeo Liu2018-04-123-1/+239
* st/va: add slice parameter handling for VP9Leo Liu2018-04-121-1/+24
* st/va: add picture parameter handling for VP9Leo Liu2018-04-121-1/+51
* st/va: add handles for VP9 buffersLeo Liu2018-04-125-2/+54
* st/va: add VP9 picture to contextLeo Liu2018-04-122-0/+5
* radeonsi: cap VP9 support to progressive bufferLeo Liu2018-04-121-0/+2
* radeonsi: cap VP9 support to RavenLeo Liu2018-04-121-0/+4
* radeon/vcn: add VP9 context bufferLeo Liu2018-04-121-0/+26
* radeon/vcn: get VP9 msg bufferLeo Liu2018-04-122-1/+176
* radeon/vcn: fill probability table to prob buffersLeo Liu2018-04-121-0/+38
* radeon/vcn: add VP9 message buffer interfaceLeo Liu2018-04-121-0/+134
* radeon/vcn: add VP9 prob table bufferLeo Liu2018-04-122-18/+37
* vl: add VP9 probability tablesLeo Liu2018-04-123-1/+588
* radeon/vcn: add VP9 dpb buffer sizeLeo Liu2018-04-121-0/+6
* radeon/vcn: add VP9 stream type for decoderLeo Liu2018-04-122-0/+4
* vl: add VP9 picture descriptionLeo Liu2018-04-121-0/+94
* vl: add VP9 profile0 and formatLeo Liu2018-04-122-2/+7
* radeonsi: correctly parse disassembly with labelsNicolai Hähnle2018-04-111-31/+32
* radeonsi: pass -O halt_waves to umr for hang debuggingNicolai Hähnle2018-04-111-2/+2
* ac/surface: don't set the display flag for obviously unsupported cases (v2)Marek Olšák2018-04-101-0/+1
* radeonsi: add shader binary padding for UMRMarek Olšák2018-04-101-3/+15
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