summaryrefslogtreecommitdiffstats
path: root/src/gallium
Commit message (Expand)AuthorAgeFilesLines
* gallium/radeon: add a proper fail path for calloc in r600_flush_from_stMarek Olšák2017-09-111-3/+6
* winsys/amdgpu: don't allow interprocess resource sharing for IBsMarek Olšák2017-09-111-1/+2
* radeonsi/gfx9: fix interprocess resource sharing on RavenMarek Olšák2017-09-111-1/+3
* r600: handle the non-TXF_LZ support path.Dave Airlie2017-09-111-1/+1
* gallium/u_blitter: use UTIL_BLITTER_ATTRIB_NONE (0) instead of 0 directlyMarek Olšák2017-09-111-2/+2
* gallium/u_blitter: don't pass GENERIC in VS if it's not neededMarek Olšák2017-09-111-17/+45
* gallium/u_blitter: use draw_rectangle for all blits except cubemapsMarek Olšák2017-09-114-92/+107
* gallium/u_blitter: use draw_rectangle callback for layered clearsMarek Olšák2017-09-116-36/+47
* gallium/u_blitter: add new union blitter_attrib to replace pipe_color_unionMarek Olšák2017-09-116-71/+72
* gallium/radeon: use rectangles for 1D and 2D texture blitsMarek Olšák2017-09-111-7/+13
* llvmpipe, draw: improve shader cache debuggingRoland Scheidegger2017-09-093-31/+59
* llvmpipe: enable PIPE_CAP_QUERY_PIPELINE_STATISTICSRoland Scheidegger2017-09-091-1/+1
* gallivm: fix gather implementation a bitRoland Scheidegger2017-09-091-10/+48
* svga: abort shader translation upon indirect indexing of temporariesCharmaine Lee2017-09-081-0/+6
* gallium/tests: use ARRAY_SIZE macroEric Engestrom2017-09-083-3/+9
* r300: use ARRAY_SIZE macroEric Engestrom2017-09-081-1/+3
* radeonsi: move the guts of ARB_shader_group_vote emission to acConnor Abbott2017-09-081-21/+3
* radeonsi: move si_emit_ballot() to acConnor Abbott2017-09-081-32/+6
* radeonsi: move emit_optimization_barrier() to acConnor Abbott2017-09-081-43/+2
* radeonsi: move llvm_get_type_size() to acConnor Abbott2017-09-081-34/+9
* Revert "st/va: add enviromental variable to disable interlace"Leo Liu2017-09-071-4/+0
* st/va: move YUV content to deinterlaced buffer when reallocated for encoderLeo Liu2017-09-071-1/+10
* st/va: reallocate the buffer if the layout isn't supportedLeo Liu2017-09-071-9/+12
* vl/compositor: make vl_compositor_set_yuv_layer() staticLeo Liu2017-09-072-44/+28
* st/omx: use vl/compositor helper function for YUV deinterlacingLeo Liu2017-09-071-30/+2
* vl/compositor: make a helper function for YUV deinterlacingLeo Liu2017-09-072-0/+40
* ac/surface: add radeon_surf::has_stencil for convenienceMarek Olšák2017-09-078-11/+12
* radeonsi: don't read tcs_out_lds_layout.patch_stride from an SGPRMarek Olšák2017-09-071-6/+14
* radeonsi: don't read tcs_out_lds_layout.vertex_size from an SGPRMarek Olšák2017-09-073-6/+20
* radeonsi/gfx9: don't read LS out vertex stride from an SGPR in monolithic HSMarek Olšák2017-09-072-1/+11
* radeonsi: don't read the LS output vertex stride from an SGPR in LSMarek Olšák2017-09-071-4/+21
* radeonsi: don't read the number of TCS out vertices from an SGPR in TCSMarek Olšák2017-09-071-2/+15
* radeonsi: don't always apply the PrimID instancing bug workaround on SIMarek Olšák2017-09-071-1/+1
* radeonsi: remove 2 callbacks from si_shader_contextMarek Olšák2017-09-073-17/+13
* winsys/amdgpu: disable local BOs on RavenMarek Olšák2017-09-071-1/+2
* llvmpipe, tgsi: hook up dx10 gather4 opcodeRoland Scheidegger2017-09-072-8/+25
* llvmpipe, draw: increase shader cache limitsRoland Scheidegger2017-09-072-4/+2
* radeon/uvd: fix the assertion check for YUYV formatLeo Liu2017-09-061-3/+5
* swr/rast: FE/Clipper - unify SIMD8/16 functions using simdlib typesTim Rowley2017-09-063-1189/+446
* swr/rast: Remove use of C++14 template variableTim Rowley2017-09-062-6/+14
* swr/rast: SIMD16 FE remove templated immediates workaroundTim Rowley2017-09-061-90/+20
* swr/rast: SIMD16 PA - rename Assemble_simd16 to AssembleTim Rowley2017-09-063-31/+15
* swr/rast: FE/Binner - unify SIMD8/16 functions using simdlib typesTim Rowley2017-09-065-1739/+696
* swr/rast: Removed some trailing whitespace caught during reviewTim Rowley2017-09-063-10/+10
* swr: set caps for VB 4-byte alignmentTim Rowley2017-09-061-3/+6
* swr/rast: Allow gather of floats from fetch shader with 2-4GB offsetsTim Rowley2017-09-062-1/+7
* radeonsi/gfx9: proper workaround for LS/HS VGPR initialization bugNicolai Hähnle2017-09-065-24/+85
* amd/common: pass chip_class to ac_dump_regNicolai Hähnle2017-09-061-15/+30
* radeonsi/gfx9: always flush DB metadata on framebuffer changesNicolai Hähnle2017-09-063-4/+14
* svga: move index buffer bind flag assertionCharmaine Lee2017-09-051-3/+3