| Commit message (Collapse) | Author | Age | Files | Lines |
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We can just support them the same way we do load_const's SSA values.
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Since we just pulled it out of the destination as 8-bit unorm, we know
it's in [0, 1] already.
shader-db:
total instructions in shared programs: 100040 -> 98208 (-1.83%)
instructions in affected programs: 14084 -> 12252 (-13.01%)
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Previously, SFU values always moved to a temporary, and TLB color reads
and texture reads always lived in r4. Instead, we can have these results
just be normal temporaries, and the register allocator can leave the
values in r4 when they don't interfere with anything else using r4.
shader-db results:
total instructions in shared programs: 100809 -> 100040 (-0.76%)
instructions in affected programs: 42383 -> 41614 (-1.81%)
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needed for MRT
Signed-off-by: Rob Clark <[email protected]>
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Signed-off-by: Rob Clark <[email protected]>
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Both a3xx and a4xx need the same logic to decide if half-precision can
be used for blit shaders. So move it to core and simplify things a bit
with a helper that considers all render targets.
Signed-off-by: Rob Clark <[email protected]>
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Collapse dirty/reading bools into status bitmask (and drop writing which
should really be the same as dirty). And use 'used_resources' list for
all tracking, including zsbuf/cbufs, rather than special casing the
color and depth/stencil buffers.
Signed-off-by: Rob Clark <[email protected]>
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Should be in units of components, not vec4's
Signed-off-by: Rob Clark <[email protected]>
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We hard-coded 4 or 8 as the max in various places. Switch it all to a
define since the limit will go up with a4xx (and maybe even again in the
future?)
Signed-off-by: Rob Clark <[email protected]>
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vl/vl_mpeg12_bitstream.c: In function 'decode_slice':
vl/vl_mpeg12_bitstream.c:928:19: warning: unused variable 'extra' [-Wunused-variable]
unsigned extra = vl_vlc_get_uimsbf(&bs->vlc, 1);
^
Signed-off-by: Vinson Lee <[email protected]>
Reviewed-by: Christian König <[email protected]>
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To circumvent a problem occuring when LINEAR_ALIGNED array mode is
selected on a TEXTURE_2D RAT.
This configuration causes MEM_RAT STORE_TYPED to write to incorrect
locations.
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Read-only and write-only image arguments are recognized and
distinguished.
Attributes of the image arguments are passed to the kernel as implicit
arguments.
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Fixed by the CB_SHADER_MASK fix.
Tested-by: Dieter Nützel <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
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This fixes the single-sample fast clear hang.
Cc: 10.6 <[email protected]>
Tested-by: Dieter Nützel <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
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No effect, but this is what we should be doing.
Tested-by: Dieter Nützel <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
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Picked from the amdgpu branch.
Reviewed-by: Michel Dänzer <[email protected]>
Reviewed-by: Christian König <[email protected]>
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We must have versioned library in mesa.icd, because ICD loader would
fail if the mesa-devel package wasn't installed.
Cc: "10.6" <[email protected]>
Reported-by: Fabian Deutsch <[email protected]>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73512
Signed-off-by: Igor Gnatenko <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
Acked-by: Michel Dänzer <[email protected]>
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Earlier commit added an extra dup(fd) to fix a ZaphodHeads issue.
Although it did not consider the (very unlikely) case where we might end
up with the valid fd == 0.
Fixes: 28dda47ae4d(winsys/radeon: Use dup fd as key in drm-winsys hash
table to fix ZaphodHeads.)
Cc: 10.6 <[email protected]>
Signed-off-by: Emil Velikov <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Mario Kleiner <[email protected]>
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This reverts commit 8559f6ce62a9d5b52fa8189ba2352cd48bdabccf.
It causes hangs in DOTA 2 Reborn.
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Reviewed-by: Francisco Jerez <[email protected]>
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lp_bld_tgsi_soa.c: In function 'lp_emit_immediate_soa':
lp_bld_tgsi_soa.c:3065:18: warning: unused variable 'size' [-Wunused-variable]
const uint size = imm->Immediate.NrTokens - 1;
^
Signed-off-by: Vinson Lee <[email protected]>
Reviewed-by: Brian Paul <[email protected]>
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Disabling the FP16 mode didn't help.
If needed, we can use this trick for blits too, but not for scaled blits.
+ 4 piglits
Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Michel Dänzer <[email protected]>
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Broken since:
46b2b3b - radeonsi: don't change pipe_resource in resource_copy_region
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91444
Reviewed-and-Tested-by: Michel Dänzer <[email protected]>
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st/nine uses GENERIC slots greater than 60.
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Reviewed-by: Michel Dänzer <[email protected]>
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Reviewed-by: Dave Airlie <[email protected]>
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This is for shader-db and should reduce size of shader dumps.
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This will be used by the new ddebug pipe. I'm including it now to avoid
conflicts with other patches.
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There are 2 reasons for this:
- LLVM optimization passes can work with floor
- there are patterns to select v_fract from floor anyway
There is no change in the generated code.
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This reverts commit 4db985a5fa9ea985616a726b1770727309502d81.
The grass no longer disappears, which was the reason the commit was reverted.
This might affect tessellation. We'll see.
Totals from affected shaders:
SGPRS: 151672 -> 150232 (-0.95 %)
VGPRS: 90620 -> 89776 (-0.93 %)
Code Size: 3980472 -> 3920836 (-1.50 %) bytes
LDS: 67 -> 67 (0.00 %) blocks
Scratch: 1357824 -> 1202176 (-11.46 %) bytes per wave
Reviewed-by: Tom Stellard <[email protected]>
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Reviewed-by: Dave Airlie <[email protected]>
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Reviewed-by: Tom Stellard <[email protected]>
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Reviewed-by: Dave Airlie <[email protected]>
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duplicated now
Reviewed-by: Dave Airlie <[email protected]>
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This will help remove some duplicated code from radeon.
Reviewed-by: Dave Airlie <[email protected]>
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Reviewed-by: Kai Wasserbäch <[email protected]>
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The patch has a better explanation. Just a summary here:
- The CPU always uploads a whole descriptor array to previously-unused memory.
- CP DMA isn't used.
- No caches need to be flushed.
- All descriptors are always up-to-date in memory even after a hang, because
CP DMA doesn't serve as a middle man to update them.
This should bring:
- better hang recovery (descriptors are always up-to-date)
- better GPU performance (no KCACHE and TC flushes)
- worse CPU performance for partial updates (only whole arrays are uploaded)
- less used IB space (no CP_DMA and WRITE_DATA packets)
- simpler code
- hopefully, some of the corruption issues with SI cards will go away.
If not, we'll know the issue is not here.
Reviewed-by: Michel Dänzer <[email protected]>
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This also moves the vec4-to-byte-addressing math into NIR, so that
algebraic has a chance at it.
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I want to be able to inspect them from other files for lowering passes in
NIR.
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For now this is just scalarizing, but it also means we'll get to dump a
bunch of QIR-based lowering in a moment.
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For now, this just splits up store_output intrinsics to be scalars, and
drops unused outputs in the coordinate shader. My goal is to be able to
drop a bunch of my VC4-specific optimization by letting NIR handle it.
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