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* nv50: apply relocations to shader codeChristoph Bumiller2011-03-021-0/+2
| | | | | On nv50, branches are absolute, so we need to adjust them according to the shader's position in the code buffer.
* nv50: fix wrong miptree tile flags taken over from nvc0Christoph Bumiller2011-03-021-3/+0
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* nouveau: remove nouveau_stateobj.hBen Skeggs2011-03-011-316/+0
| | | | Signed-off-by: Ben Skeggs <[email protected]>
* nvc0: fix a crash on context destructionBen Skeggs2011-03-011-2/+6
| | | | Signed-off-by: Ben Skeggs <[email protected]>
* nouveau: ensure vbo_dirty is set when buffer write transfer completeBen Skeggs2011-03-0126-231/+267
| | | | | | This introduces a shared nouveau_context struct to track such things. Signed-off-by: Ben Skeggs <[email protected]>
* nouveau: fix leak of nouveau_mman structsBen Skeggs2011-03-011-0/+2
| | | | Signed-off-by: Ben Skeggs <[email protected]>
* nvc0: port to common fence/mm/buffer codeBen Skeggs2011-03-0121-1347/+128
| | | | Signed-off-by: Ben Skeggs <[email protected]>
* nv50: multiply polygon offset units by 2Ben Skeggs2011-03-011-1/+1
| | | | Signed-off-by: Ben Skeggs <[email protected]>
* nv50: sync textures with render targets ourselvesBen Skeggs2011-03-017-7/+37
| | | | | | Port of the nvc0 commit doing the same. Signed-off-by: Ben Skeggs <[email protected]>
* nv50: move onto common linear buffer managerBen Skeggs2011-03-0116-690/+74
| | | | Signed-off-by: Ben Skeggs <[email protected]>
* nouveau: common linear buffer manager, ported from nv50/nvc0 driversBen Skeggs2011-03-016-2/+638
| | | | | | | nv50_resource is being called nv04_resource now temporarily, to avoid a naming conflict with nouveau_resource from libdrm. Signed-off-by: Ben Skeggs <[email protected]>
* nouveau: create linear gart/vram mman in common screen initBen Skeggs2011-03-016-14/+19
| | | | Signed-off-by: Ben Skeggs <[email protected]>
* nouveau: fix fence_ref() where fence and *ref are the same fenceBen Skeggs2011-03-011-2/+3
| | | | Signed-off-by: Ben Skeggs <[email protected]>
* nouveau: fix compiler complaintBen Skeggs2011-03-014-2/+11
| | | | Signed-off-by: Ben Skeggs <[email protected]>
* nv50: make mm available as common codeBen Skeggs2011-03-019-70/+82
| | | | Signed-off-by: Ben Skeggs <[email protected]>
* nv50: move onto shared fence codeBen Skeggs2011-03-0110-347/+45
| | | | Signed-off-by: Ben Skeggs <[email protected]>
* nouveau: move nv50/nvc0 fencing to common location, and modify slightlyBen Skeggs2011-03-015-4/+296
| | | | | | | Modified from original to remove chipset-specific code, and to be decoupled from the mm present in said drivers. Signed-off-by: Ben Skeggs <[email protected]>
* nv50-nvc0: set cur_ctx during init if none currently boundBen Skeggs2011-03-012-0/+4
| | | | Signed-off-by: Ben Skeggs <[email protected]>
* nv50: replace most of it with nvc0 driver ported to nv50Christoph Bumiller2011-02-2841-6621/+8825
| | | | We'll have to do some unification now to reduce code duplication.
* r300g: disable hyper-z on rs6xx+Marek Olšák2011-02-281-6/+0
| | | | It doesn't work.
* rgtc: llvmpipe/softpipe refuse RGTC until u_format has support.Dave Airlie2011-02-282-0/+10
| | | | | | So far I haven't implemented the u_format code for these. Signed-off-by: Dave Airlie <[email protected]>
* r300g: force swizzles for RGTCDave Airlie2011-02-281-0/+5
| | | | still can't get signed to work
* r600g: implement instanced drawing supportChristian König2011-02-286-103/+191
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* st/mesa & v_bug_mgr: two small instanced drawing fixesChristian König2011-02-281-1/+4
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* Revert "r600g: Don't negate result of ABS instruction"Dave Airlie2011-02-281-2/+0
| | | | | | This reverts commit b6d40213935da702570eca2c0861bd4b1d7f5254. This actually breaks gears here on my rv670.
* r600g: Process TRUNC with tgis_op2Fabian Bieler2011-02-281-2/+2
| | | | | | TRUNC is neither a scalar instruction nor exclusive to the Trans unit. Signed-off-by: Dave Airlie <[email protected]>
* r600g: Don't negate result of ABS instructionFabian Bieler2011-02-281-0/+2
| | | | Signed-off-by: Dave Airlie <[email protected]>
* i915g: implement cache flushingDaniel Vetter2011-02-276-8/+62
| | | | | | | | | | | With an extremely dumb strategy. But it's the same i915c employs. Also improve the hw_atom code slightly by statically specifying the required batch space. For extremely variably stuff (shaders, constants) it would probably be better to add a new parameter to the hw_atom->validate function. Signed-off-by: Daniel Vetter <[email protected]>
* i915g: buffer validation for blitterDaniel Vetter2011-02-271-0/+11
| | | | Signed-off-by: Daniel Vetter <[email protected]>
* i915g: buffer validation for render stateDaniel Vetter2011-02-273-0/+87
| | | | | | | | Also contains the first few bits for hw state atoms. v2: Implement suggestion by Jakob Bornecrantz. Signed-off-by: Daniel Vetter <[email protected]>
* i915g/winsys: buffer validation supportDaniel Vetter2011-02-273-0/+42
| | | | | | | v2: Add the batch bo to the libdrm validation lost, for otherwise libdrm won't take previously used buffers into account. Signed-off-by: Daniel Vetter <[email protected]>
* i915g: add raw batchbuffer dumping in drm winsysDaniel Vetter2011-02-273-0/+11
| | | | | | | | | These files can be decoded with intel_dump_decode from the intel-gpu-tools available at: http://cgit.freedesktop.org/xorg/app/intel-gpu-tools/ Signed-off-by: Daniel Vetter <[email protected]>
* i915g: cleanup static state calculation, part 2Daniel Vetter2011-02-273-48/+48
| | | | | | Now also for the DRAW_RECT command Signed-off-by: Daniel Vetter <[email protected]>
* i915g: cleanup static state calculation, part 1Daniel Vetter2011-02-273-89/+103
| | | | | | | Move it to i915_state_static.c This way i915_emit_state.c only emits state and doesn't (re)calculate it. Signed-off-by: Daniel Vetter <[email protected]>
* i915g: make dynamic state emission actually lazyDaniel Vetter2011-02-261-1/+1
| | | | | | Premature semicolon. Signed-off-by: Daniel Vetter <[email protected]>
* gallivm: Initialize stack valuesJakob Bornecrantz2011-02-261-8/+8
| | | | | valgrind gives me a warning with llvmpipe with profile builds but not debug builds, this seems to fix the issue at least.
* i915g: Handle null constants properlyJakob Bornecrantz2011-02-261-3/+6
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* i915g: fix null deref in draw_rect emissionDaniel Vetter2011-02-261-4/+8
| | | | Signed-off-by: Daniel Vetter <[email protected]>
* i915g: simplify math in constants emissionDaniel Vetter2011-02-261-1/+1
| | | | | | The old code even falls apart for nr == 0 (which is caught earlier, but)! Signed-off-by: Daniel Vetter <[email protected]>
* i915g: Use the same debug env vars in drm and sw winsysJakob Bornecrantz2011-02-261-1/+1
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* i915g: Use unchecked writes in sw winsys batchbufferJakob Bornecrantz2011-02-261-3/+3
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* Check for out of memory when creating fenceAlan Hourihane2011-02-261-0/+3
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* util: Don't destroy shaders null shadersJakob Bornecrantz2011-02-261-2/+4
| | | | Fixes regression from a08e612fd8e7ca2ac2fef8961e56e5b094033717
* util: Don't create array texture shaders if the driver doesn't support itJakob Bornecrantz2011-02-261-4/+6
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* gallium/tgsi: shuffle ureg_src structure to work around gcc4.6.0 issueJerome Glisse2011-02-251-14/+14
| | | | | | | | | | | | There is an issue with gcc 4.6.0 that leads to segfault/assert with mesa due to ureg_src size, reshuffling the structure member to better better alignment work around the issue. http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47893 7.9 + 7.10 candidate Signed-off-by: Jerome Glisse <[email protected]>
* gallium/util: add 1d/2d mipmap generation supportDave Airlie2011-02-251-6/+37
| | | | | | | | so far only hw mipmap generation is testing on softpipe, passes test added to piglit. this requires another patch to mesa to let array textures mipmaps even start to happen.
* scons: Reduce all Cygwin platform names to 'cygwin'.Vinson Lee2011-02-241-1/+1
| | | | | | | | | | | platform.system in SCons on Cygwin includes the OS version number. Windows XP - CYGWIN_NT-5.1 Windows Vista - CYGWIN_NT-6.0 Windows 7 - CYGWIN_NT-6.1 Reduce all Cygwin platform variants to just 'cygwin' so anything downstream can simply use 'cygwin' instead of the different full platform names.
* r600g: explicity set sign bits for RGTCDave Airlie2011-02-251-2/+4
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* r600g: bc 4/5 or rgtc textures need to be tiled as well.Dave Airlie2011-02-252-10/+10
| | | | | | Make the s3tc upload code more generic. Signed-off-by: Dave Airlie <[email protected]>
* r300g: explicit sign bits on RGTC texturesDave Airlie2011-02-251-2/+4
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