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* vc4: Fix triangle-guardband-viewport piglit test.Eric Anholt2014-12-111-5/+14
* vc4: Fix a memory leak in setting up QPU instructions for scheduling.Eric Anholt2014-12-111-1/+2
* draw: simplify prim id insertion in prim assemblerRoland Scheidegger2014-12-101-34/+5
* draw: fix another decompose bug affecting constant interpolated attributesRoland Scheidegger2014-12-101-2/+1
* draw: fix flatshade stage for constant interpolated valuesRoland Scheidegger2014-12-103-69/+126
* draw: copy over prim id header in flatshade stage when emitting linesRoland Scheidegger2014-12-101-3/+6
* gallium/docs: clarify fragment shader position input w component.Roland Scheidegger2014-12-101-2/+4
* radeonsi: take into account NULL colorbuffers when computing CB_TARGET_MASKMarek Olšák2014-12-101-4/+12
* radeonsi: only emit line stippling and provoking vertex state when it changesMarek Olšák2014-12-105-0/+9
* radeonsi: fix SPI state dependency on sprite_coord_enableMarek Olšák2014-12-102-2/+4
* radeonsi: fix line stippling and provoking vertex state for GS primitivesMarek Olšák2014-12-101-1/+3
* radeonsi: emit DRAW_PREAMBLE only if it changesMarek Olšák2014-12-103-8/+17
* radeonsi: remove setting of VGT_DISPATCH_DRAW_INDEXMarek Olšák2014-12-101-3/+0
* radeonsi: emit GS_OUT_PRIM_TYPE only if it changesMarek Olšák2014-12-103-1/+6
* radeonsi: emit primitive restart only if it changesMarek Olšák2014-12-103-5/+22
* radeonsi: emit base vertex and start instance only if they changeMarek Olšák2014-12-103-3/+38
* radeonsi: emit clip registers only if VS, GS, or rasterizer is changedMarek Olšák2014-12-105-32/+39
* radeonsi: get info about VS outputs from tgsi_shader_infoMarek Olšák2014-12-103-35/+34
* radeonsi: move all shader-related functions to a new file si_state_shaders.cMarek Olšák2014-12-106-785/+810
* radeonsi: generate derived and draw-related registers directly in the CSMarek Olšák2014-12-103-75/+76
* radeonsi: si_conv_pipe_prim shouldn't failMarek Olšák2014-12-101-11/+3
* radeonsi: remove useless variable si_context::pm4_dirty_cdwordsMarek Olšák2014-12-103-11/+1
* radeonsi: remove unused draw packet functionsMarek Olšák2014-12-102-87/+0
* radeonsi: emit draw packets directly into the CSMarek Olšák2014-12-103-68/+95
* radeonsi: add emit util functions for SH registersMarek Olšák2014-12-102-1/+18
* tgsi: add tgsi_shader_info::writes_clipvertexMarek Olšák2014-12-102-0/+4
* tgsi: add clip and cull distance writemasks into tgsi_shader_infoMarek Olšák2014-12-102-0/+6
* tgsi: add tgsi_shader_info::writes_psizeMarek Olšák2014-12-102-0/+4
* cso: put cso_release_all into cso_destroy_contextMarek Olšák2014-12-108-32/+7
* gallium/target: Haiku softpipeAlexander von Gluck IV2014-12-101-1/+1
* gallium/aux: Avoid redefining MAXAlexander von Gluck IV2014-12-101-0/+2
* clover: Use switch when creating kernel arguments.Jan Vesely2014-12-101-25/+19
* r600g: only init GS_VERT_ITEMSIZE on r600Dave Airlie2014-12-101-5/+2
* vc4: Do QPU scheduling across uniform loads.Eric Anholt2014-12-091-28/+60
* vc4: Populate the delay field better, and schedule high delay first.Eric Anholt2014-12-091-1/+49
* vc4: Skip raddr dependencies for 32-bit immediate loads.Eric Anholt2014-12-091-2/+5
* vc4: Mark VPM read setup as impacting VPM reads, not writes.Eric Anholt2014-12-091-1/+7
* vc4: Refuse to merge instructions involving 32-bit immediate loads.Eric Anholt2014-12-091-0/+5
* clover: Fix build after llvm r223802Aaron Watry2014-12-091-0/+4
* freedreno/a4xx: frag-coord / face fixesRob Clark2014-12-091-6/+19
* freedreno/a4xx: fix rendering to layer != 0Rob Clark2014-12-091-1/+4
* freedreno/a4xx: temp hack for FLAT varyingsRob Clark2014-12-091-0/+19
* freedreno/ir3: lower TXP as neededRob Clark2014-12-093-3/+19
* freedreno/a4xx: XA gpu hang at startupRob Clark2014-12-092-1/+9
* freedreno/a4xx: texture fixesRob Clark2014-12-096-7/+54
* freedreno: cleanup slice alignment/setupRob Clark2014-12-091-36/+14
* freedreno: update generated headersRob Clark2014-12-096-18/+65
* tgsi/lowering: add support to lower TXP (v2)Rob Clark2014-12-092-15/+34
* draw: implement TGSI_PROPERTY_VS_WINDOW_SPACE_POSITIONMarek Olšák2014-12-0910-11/+49
* vc4: Reserve rb31 instead of r3 for raddr conflict spills.Eric Anholt2014-12-092-11/+45
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