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* i915g: add a few more render target formatsDaniel Vetter2011-06-131-0/+7
| | | | | | Snatched from xvmc. Signed-off-by: Daniel Vetter <[email protected]>
* r600g: Put shaders into immutable buffers.Mathias Fröhlich2011-06-132-2/+3
| | | | | | Put the shader programs into an immutable buffer object. Also make sure that those object can be taken from the user space buffer object pool.
* r600g: Allow VRAM for the initial domain for every buffer binding.Mathias Fröhlich2011-06-131-15/+11
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* r600g: Set the domains value also for recycled buffer objects.Mathias Fröhlich2011-06-131-12/+14
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* r600g: Fix typo.Mathias Fröhlich2011-06-131-1/+1
| | | | Fix an obvious typo in the yet unused part of the shader setup.
* r600g: remove useless call to u_upload_flushPierre-Eric Pelloux-Prayer2011-06-131-5/+0
| | | | | | | | | | | | | | | | | | No regressions found with : - piglit (quick.tests) - Unigine Heaven - Lightsmark - openarena - Imprudence (Second Life fork) agd5f Note: this patch was previously reverted due to piglit regressions, but I'm not able to reproduce them here. See this bug: https://bugs.freedesktop.org/show_bug.cgi?id=34008 and discussion: http://lists.freedesktop.org/archives/dri-devel/2011-June/011996.html Signed-off-by: Alex Deucher <[email protected]>
* r600g: fixed bo memory leak issuePierre-Eric Pelloux-Prayer2011-06-131-0/+1
| | | | | pipe_resource_reference call was miossing, thus creating massive memory under certain conditions. Fix : https://bugs.freedesktop.org/show_bug.cgi?id=37168
* st/eglwayland: Add support for EGL_DEFAULT_DISPLAYBenjamin Franzke2011-06-124-0/+15
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* r300g: max_anisotropy of 1 is not anisotropic filteringMarek Olšák2011-06-111-1/+1
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* i915g: implement fence signallingDaniel Vetter2011-06-111-2/+6
| | | | | | v2: Incorporated feedback from Jakob Bornecrantz. Signed-off-by: Daniel Vetter <[email protected]>
* r600g: VGT_PRIMITIVE_TYPE is specialAlex Deucher2011-06-092-3/+3
| | | | | | | It's a special reg and does not require a flush like the other CONFIG regs. Signed-off-by: Alex Deucher <[email protected]>
* r600g: Handle CONFIG regs properlyAlex Deucher2011-06-092-32/+31
| | | | | | | | | | CONFIG regs (byte offsets 0x8000-0xac00) are single state and the pipeline must be flushed and hw idle when they are changed. Border color regs are in the CONFIG range and this is why a flush is required when changing them. CONTEXT regs (byte offset 0x28000+) are multi-state and those do not require flushes when changing them. Signed-off-by: Alex Deucher <[email protected]>
* r300g: fix texturing with non-3D textures and wrap R mode set to sample borderMarek Olšák2011-06-091-0/+6
| | | | | | | | | | If the wrap R (3rd) mode is set to CLAMP or CLAMP_TO_BORDER and the texture isn't 3D, r300 always samples the border color regardless of texture coordinates. I HATE THIS HARDWARE. NOTE: This is a candidate for the 7.10 branch.
* r300g: don't enable aniso with nearest filteringMarek Olšák2011-06-091-41/+39
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* r600g: adjust vs/ps gprs on r600/r700 cards when needed.Dave Airlie2011-06-095-19/+77
| | | | | | | | | | | | | | | Ideally we'd have a compiler and register spilling and all that but this is good enough for now to avoid the gpu hang in piglit, glsl-vs-vec4-indexing-temp-dst-in-nested-loop-combined on r600/r700 cards. based on r600c patch Andre Maasikas <[email protected]> r600c: bump sq gpr resources if a shader needs more than default Signed-off-by: Dave Airlie <[email protected]>
* r600g: remove unused variableMarek Olšák2011-06-091-1/+0
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* r300g: fix draw_vbo splitting on r3xx-r4xxMarek Olšák2011-06-091-5/+10
| | | | NOTE: This is a candidate for the 7.10 branch.
* r300g: make translate_primitive table-drivenMarek Olšák2011-06-091-24/+20
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* util: fix strict aliasing issues in u_format_r11g11b10f.hRoland Scheidegger2011-06-091-8/+16
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* util: add gcc version check for builtinsRoland Scheidegger2011-06-091-3/+3
| | | | | Looks like only next_power_of_two, logbase2 and bitcount use builtins requiring gcc 3.4, so maybe everything else compiles with older gcc.
* util: better logbase2/next_power_of_two implementationsBenjamin Bellec2011-06-091-8/+24
| | | | | Use __builtin_clz when available for logbase/next_power_of_two, and replace next_power_of_two with faster implementation otherwise.
* glx/xlib: Handle glXCreateContextAttribsARB in glXGetProcAddress.José Fonseca2011-06-081-0/+3
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* svga: fix typos, update commentsBrian Paul2011-06-081-7/+5
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* st/egl: set EGL_ALPHA_MASK_SIZEChia-I Wu2011-06-091-0/+4
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* r600g: fix mixup in GPR resource reg setupAlex Deucher2011-06-081-3/+10
| | | | | | | GLOBAL_GPR regs should be 0. Need to set the number of temp regs in SQ_GPR_RESOURCE_MGMT_1. Signed-off-by: Alex Deucher <[email protected]>
* gallium: fix comments for pipe_stream_output_stateBrian Paul2011-06-081-7/+9
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* gallium: s/bool/boolean/Brian Paul2011-06-0813-21/+21
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* draw: fix edge flag handling in clipper (for unfilled tris/quads/polygons)Brian Paul2011-06-081-5/+57
| | | | | | | | | | | | | | | | | | | | Previously, we were errantly drawing some interior edges of clipped polygons and quads. Also, we were introducing extra edges where polygons intersected the view frustum clip planes. The main problem was that we were ignoring the edgeflags encoded in the primitive header's 'flags' field which are set during polygon/quad ->tri decomposition. We need to observe those during clipping. Since we can't modify the existing vert's edgeflag fields, we need to store them in a parallel array. Edge flags also need to be handled differently for view frustum planes vs. user-defined clip planes. In the former case we don't want to draw new clip edges but in the later case we do. This matches NVIDIA's behaviour and it just looks right. Finally, note that the LLVM draw code does not properly set vertex edge flags. It's OK on the regular software path though.
* r600g: missed one line in eg dyn gpr fallback.Dave Airlie2011-06-081-0/+1
| | | | | | need more sleep or something. Signed-off-by: Dave Airlie <[email protected]>
* r600g: set enable always bits for r600/r700 sq registers.Dave Airlie2011-06-081-11/+11
| | | | | | This makes sure these are enabled even if set to 0 at startup. Signed-off-by: Dave Airlie <[email protected]>
* r600g: condition evergreen dyn gpr resource managementDave Airlie2011-06-082-2/+33
| | | | | | | So only with kernel version 2.7 can this work, thanks to Alex for pointing that out. Also add a workaround for a hw bug. Signed-off-by: Dave Airlie <[email protected]>
* r600g: fix warnings in winsys.Dave Airlie2011-06-081-5/+2
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600g: enable dynamic GPR resource management on evergreenDave Airlie2011-06-083-20/+11
| | | | | | | | | | | Evergreen can do this as well as cayman, so we should enable it. This fixes a gpu lockup with glsl-vs-vec4-indexing-temp-dst-in-nested-loop-combined.shader_test I need to add a better workaround for r600/r700. Signed-off-by: Dave Airlie <[email protected]>
* r600g: only add blocks once to the dirty/enabled lists.Dave Airlie2011-06-081-3/+5
| | | | | | This caused a loop in some tests. Signed-off-by: Dave Airlie <[email protected]>
* r600g: fix regression in recent state changes.Dave Airlie2011-06-081-0/+1
| | | | | | | | | | We weren't emitting the SQ setup regs at all which really is fail. When a state is always enabled we need to add it to the dirty list as well. Signed-off-by: Dave Airlie <[email protected]>
* r600g: move simple part of bo reloc processing inline.Dave Airlie2011-06-082-12/+17
| | | | | | | This just moves the messy stuff out of the fast path, and leaves the fast-case in the fast path. Signed-off-by: Dave Airlie <[email protected]>
* r600g: take alpha ref update out of line.Dave Airlie2011-06-081-5/+4
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600g: split resource emit path from main register emit pathDave Airlie2011-06-084-17/+106
| | | | | | | | | Since resources don't generally vary in size, this splits the emit path, it also takes into a/c that texture and vertex resources have different number of relocs, and avoids emitting the extra reloc for vertex resources. Signed-off-by: Dave Airlie <[email protected]>
* r600g: exit bo per reg scanning loop early.Dave Airlie2011-06-082-9/+13
| | | | | | | | | Exit this loop early to avoid pointless iterations later. Move the resource bos to the first two regs, it actually doesn't matter which regs we use for this in resource land. Signed-off-by: Dave Airlie <[email protected]>
* r600g: reorder evergreen draw packets to be smaller.Dave Airlie2011-06-081-4/+8
| | | | | | | We were always re-emitting lots of unnecessary changes here, avoid doing that. Signed-off-by: Dave Airlie <[email protected]>
* r600g: inline r600_bo_reference.Dave Airlie2011-06-083-13/+15
| | | | | | This relies on the reference member being first, so document it. Signed-off-by: Dave Airlie <[email protected]>
* r600g: no need to drop the references here.Dave Airlie2011-06-081-2/+0
| | | | | | We drop them when we reference the new objects in the next line. Signed-off-by: Dave Airlie <[email protected]>
* r600g: use memcmp instead of a loop in state_set_resourceDave Airlie2011-06-081-5/+3
| | | | Signed-off-by: Dave Airlie <[email protected]>
* r600g : fix incorrect size computation in r600_query_resultPierre-Eric Pelloux-Prayer2011-06-071-1/+2
| | | | | | | | | | | | | query->num_results already has the size in dwords of the query buffer. There no need to multiply again. We were reading past the end of the buffer, resulting in reading garbage. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=37028 agd5f: clarify the comment. Signed-off-by: Alex Deucher <[email protected]>
* r600g: remove pre-r6xx asic families and pci idsAlex Deucher2011-06-072-35/+0
| | | | | | Not sure why these were included originally. Signed-off-by: Alex Deucher <[email protected]>
* r600g: always clear query memoryAlex Deucher2011-06-071-3/+3
| | | | | | | | | | | | | According to the hw documentation, the driver needs to: - allocate 128 bits for each possible DB - clear the 128 bits for each possible DB - write 1 to bits 127 and 63 for upper DBs that don't exist on a particular asic Previously we were only doing these steps if the asic had less than the max possible DBs. Signed-off-by: Alex Deucher <[email protected]>
* r300g: consolidate deducing chipset infoMarek Olšák2011-06-074-392/+107
| | | | Use the new PCI ID table, make it simpler.
* r600g: add missing r300 familiesMarek Olšák2011-06-071-0/+5
| | | | Wondering why r600g needs to include r300_pci_ids.h
* r300g: Remove is_r3xxBenjamin Franzke2011-06-073-215/+9
| | | | | | Use r300_pci_ids.h instead. Reviewed-by: Alex Deucher <[email protected]>
* r600g: Use radeon pciid list for the family lookup tableBenjamin Franzke2011-06-072-481/+6
| | | | Reviewed-by: Alex Deucher <[email protected]>
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