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* radeon/llvm: Remove AMDIL ADD instructionsTom Stellard2012-05-246-179/+4
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* radeon/llvm: Remove AMDIL binary instrutions (OR, AND, XOR, NOT)Tom Stellard2012-05-248-422/+8
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* radeon/llvm: Remove AMDILMachinePeephole passTom Stellard2012-05-244-177/+0
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* radeon/llvm: Remove AMDIL CMP instructions and associated lowering codeTom Stellard2012-05-243-661/+22
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* radeon/llvm: Remove AMDIL ROUND_NEAREST instructionTom Stellard2012-05-244-6/+6
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* radeon/llvm: Remove AMDIL ROUND_POSINF instructionTom Stellard2012-05-244-6/+10
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* radeon/llvm: Add custom SDNode for FRACTTom Stellard2012-05-246-6/+10
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* radeon/llvm: Use -1 as true value for SET* integer instructionsTom Stellard2012-05-243-32/+28
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* radeon/llvm: Handle SETGE_INT, SETGE_UINT, and SETGT_UINT opcodesTom Stellard2012-05-241-0/+6
| | | | | Support for these was inadvertently dropped in commit cee23ab246f22210b3063cdc47bdb45b3d943526
* radeon/llvm: Avoid error with SI in EmitInstrWithCustomInserter()Tom Stellard2012-05-241-0/+1
| | | | | | We need to return immediately after inserting instructions that require S_WAITCNT so that the parent class' custom inserter won't try to insert them again.
* tgsi: Initialize Padding struct fields.Vinson Lee2012-05-231-0/+4
| | | | | | | Fix uninitialized scalar variable defects report by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* llvmpipe: Fix alpha testing precision on rgba8 formats.José Fonseca2012-05-223-1/+34
| | | | | | | | | | This is a long standing problem, that recently surfaced with the change to enable perspective correct color interpolation. A fix for all possible formats is left to the future. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* scons: Do not build glx and egl on Cygwin.Vinson Lee2012-05-221-2/+2
| | | | | Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* nv30: check for NULL vertex buffers in prevalidate_vbufsChristoph Bumiller2012-05-221-1/+1
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* nv50: make unaligned index buffer offsets work againChristoph Bumiller2012-05-221-1/+3
| | | | Messed up in ef7bb281292c17b762b57779306e874704c87328.
* nvc0: don't set NEW_IDXBUF in nvc0_switch_pipe_context if none is boundChristoph Bumiller2012-05-221-0/+2
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* llvmpipe: Added a error counter to lp_test_conv.James Benton2012-05-211-3/+7
| | | | | | Useful for keeping track of progress when fixing errors! Signed-off-by: José Fonseca <[email protected]>
* llvmpipe: Changed known failures in lp_test_conv.James Benton2012-05-211-3/+9
| | | | | | To comply with the recent fixes to lp_bld_conv. Signed-off-by: José Fonseca <[email protected]>
* llvmpipe: Added fixed point types tests to lp_test_conv.James Benton2012-05-211-6/+7
| | | | Signed-off-by: José Fonseca <[email protected]>
* gallivm: Fixed erroneous optimisation in lp_build_min/max.James Benton2012-05-211-7/+14
| | | | | | | | Previously assumed normalised was 0 to 1, but it can be -1 to 1 if type is signed. Tested with lp_test_conv and lp_test_format, reduced errors. Signed-off-by: José Fonseca <[email protected]>
* gallivm: Compensate for lp_const_offset in lp_build_conv.James Benton2012-05-211-4/+31
| | | | | | | Fixing a /*FIXME*/ to remove errors in integer conversion in lp_build_conv. Tested using lp_test_conv and lp_test_format, reduced errors. Signed-off-by: José Fonseca <[email protected]>
* gallivm: Fixed overflow in lp_build_clamped_float_to_unsigned_norm.James Benton2012-05-211-1/+1
| | | | | | Tested with lp_test_conv and lp_test_format, reduced errors. Signed-off-by: José Fonseca <[email protected]>
* radeon/llvm: Handle selectcc DAG nodeTom Stellard2012-05-207-54/+350
| | | | | R600 can now select instructions from the selectcc DAG node, which is typically lowered to one of the SET* instructions.
* svga: whitespace, comments, formatting clean-upsBrian Paul2012-05-191-38/+31
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* svga: return PIPE_OK instead of 0Brian Paul2012-05-195-11/+11
| | | | And fix the emit_rss() function's return type.
* svga: fix zero-stride vertex array bugBrian Paul2012-05-191-2/+6
| | | | | | | | | | | | | | For zero-stride vertex arrays, the svga driver copies the value into the constant value and uses that value in the shader. The recent gallium-userbuf changes caused a regression in this. An example symptom was per-primitive glColor3f() calls getting ignored. Where we copied the vertex value from the vertex buffer to the constant buffer we neglected to take into account the pipe_vertex_buffer::buffer_offset field. Adding that value to the source offset fixes the problem. Actually, it looks like we should have been doing this all along, but it never was an issue before for some reason.
* radeonsi: Only honour point related rasterizer state when rendering points.Michel Dänzer2012-05-181-2/+3
| | | | Avoids hangs when not rendering points.
* radeonsi: Fix parameter cache offsets for fragment shader inputs.Michel Dänzer2012-05-183-2/+4
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* gallium/tgsi/text: Ensure ret is initialized in parse_immediate_data.Vinson Lee2012-05-171-0/+4
| | | | | | | Fix uninitialized scalar variable defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radeon/llvm: Fix segfault while lowering lrp intrinsicTom Stellard2012-05-171-2/+3
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* radeon/llvm: Add DAG nodes for MIN instructionsTom Stellard2012-05-176-14/+38
| | | | Also, remove the AMDIL MIN* instruction defs.
* llvmpipe: Avoid adding floating point zero to flat inputs.José Fonseca2012-05-181-1/+4
| | | | | Which could clobber integer inputs, if the addition is not optimized away (e.g., if optimizations are disabled for debugging purposes).
* Fix fetching integer inputs.José Fonseca2012-05-181-0/+8
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* llvmpipe: Implement TXQ.Olivier Galibert2012-05-187-6/+227
| | | | | | | | | | Piglits test for fragment shaders pass, vertex shaders fail. The actual failure seems to be in the interpolators, and not the textureSize query. Signed-off-by: Olivier Galibert <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* llvmpipe: Don't mess with the provoking vertex when inverting a triangle.Olivier Galibert2012-05-181-5/+40
| | | | | | | Fixes a bunch of piglit tests related to flat interpolation of floats. Signed-off-by: Olivier Galibert <[email protected]> Signed-off-by: José Fonseca <[email protected]>
* radeon/llvm: Lower lrp intrinsic during ISelTom Stellard2012-05-173-7/+19
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* radeon/llvm: Remove AMDIL MAD instruction defsTom Stellard2012-05-176-7/+14
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* radeon/llvm: Remove AMDIL MUL_IEEE* instructionsTom Stellard2012-05-173-7/+3
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* r600g: Handle MUL_IEEE in r600_bytecode_get_num_operandsTom Stellard2012-05-171-0/+2
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* radeon/llvm: Expand fsub during ISelTom Stellard2012-05-172-11/+2
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* radeon/llvm: Remove AMDIL floating-point ADD instruction defsTom Stellard2012-05-175-8/+9
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* radeon/llvm: Remove AMDIL CMOVLOG* instruction defsTom Stellard2012-05-174-26/+6
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* radeon/llvm: Move lowering of ABS_i32 to ISelTom Stellard2012-05-174-17/+16
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* radeon/llvm: Remove sub patterns from AMDILInstrPatterns.tdTom Stellard2012-05-172-21/+1
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* radeon/llvm: Add custom SDNodes for MAXTom Stellard2012-05-1710-10/+108
| | | | | We now lower the various intrinsics for max to SDNodes and then use tablegen patterns to lower the SDNodes to instructions.
* nouveau: place static buffers in VRAM if preferred by the driverChristoph Bumiller2012-05-176-12/+62
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* nv50/ir: fix reversed order of lane ops in quadopsChristoph Bumiller2012-05-172-4/+6
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* nv50,nvc0: handle user vertex buffersChristoph Bumiller2012-05-1714-308/+423
| | | | And restructure VBO validation a little in the process.
* nv50,nvc0: handle user index buffersChristoph Bumiller2012-05-178-47/+49
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* nv50,nvc0: handle user constbufs without wrapping them in a resourceChristoph Bumiller2012-05-1714-165/+201
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