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* gallium/radeon: rename write_*_reg functionsMarek Olšák2015-09-0111-220/+220
| | | | | | | | e.g. radeon_set_context_reg is nicer and looks consistent next to radeon_emit(). Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: rename and precalculate polygon offset statesMarek Olšák2015-09-012-40/+45
| | | | | | | one less calloc and state construction while drawing Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: convert CB_TARGET_MASK setup to an atomMarek Olšák2015-09-015-17/+13
| | | | | Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: don't set VGT_VTX_CNT_EN twice in init_configMarek Olšák2015-09-011-1/+0
| | | | | Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: convert stencil ref state into an atomMarek Olšák2015-09-015-39/+50
| | | | | Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: convert blend color state into an atomMarek Olšák2015-09-014-9/+20
| | | | | Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: convert sample mask state into an atomMarek Olšák2015-09-016-19/+25
| | | | | Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: convert clip state into an atomMarek Olšák2015-09-014-14/+19
| | | | | | | Reducing calloc overhead. Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: avoid redundant CB and DB register updatesMarek Olšák2015-09-017-12/+36
| | | | | | | | | | The main idea is to avoid setting CB_COLORi_INFO = 0 for i>0 repeatedly when those colorbuffers aren't used. This is mainly for glamor. Same for DB. Z_INFO and STENCIL_INFO need to be cleared only once. Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: don't rebind GSVS ring buffers every draw call using GSMarek Olšák2015-09-013-3/+10
| | | | | Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: don't clear the tessellation factor ring bufferMarek Olšák2015-09-011-2/+0
| | | | | | | Leftover from the bring-up. Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: remove the tf_ring state, add the registers to init_configMarek Olšák2015-09-014-15/+13
| | | | | | | One less state to worry about. Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: remove the gs_rings state, add the registers to init_configMarek Olšák2015-09-014-16/+14
| | | | | Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: use a bitmask for tracking dirty atomsMarek Olšák2015-09-013-13/+18
| | | | | | | | This mainly removes the cache misses when checking the dirty flags. Not much else though. Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: initialize atom IDs for external atomsMarek Olšák2015-09-012-4/+13
| | | | | Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: call si_init_atom for remaining radeonsi atomsMarek Olšák2015-09-018-41/+29
| | | | | | | | | | I need to initialize more atom IDs. This adds 4 more si_init_atom calls, which simplifies the code. (si_init_atom needs a different context type of the emit functions though) Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: initialize atom IDsMarek Olšák2015-09-011-6/+8
| | | | | Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: define the state atom array separatelyMarek Olšák2015-09-014-21/+23
| | | | | Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: optimize viewport statesMarek Olšák2015-09-016-26/+54
| | | | | | | same as scissors Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: optimize scissor statesMarek Olšák2015-09-018-27/+79
| | | | | | | | | - convert 16 states to 1 atom - only emit 1 scissor if VIEWPORT_INDEX isn't written - use only one packet when emitting consecutive scissors Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: add SI_MAX_ATTRIBSMarek Olšák2015-09-012-5/+6
| | | | | | | PIPE_MAX_ATTRIBS is 32, but we currently only support 16. Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: fix memory usage checking for big IBsMarek Olšák2015-09-011-8/+9
| | | | | | Cc: 11.0 <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: set all 16 viewport Z bounds for GL 4.1Marek Olšák2015-09-011-2/+6
| | | | | | Cc: 11.0 <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* radeonsi: fix a Unigine Heaven hang when drirc is missingMarek Olšák2015-09-014-1/+28
| | | | | | Cc: 10.6 11.0 <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* winsys/amdgpu: use small IBs for better performance on VIMarek Olšák2015-09-011-7/+9
| | | | | Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* gallium/util: add u_bit_scan_consecutive_rangeMarek Olšák2015-09-011-0/+20
| | | | | Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]>
* r600g: fix calculation for gpr allocationDave Airlie2015-09-011-1/+1
| | | | | | | | | | | | | | | I've been chasing a geom shader hang on rv635 since I wrote r600 geom code, and finally I hacked some values from fglrx in and I could run texelfetch without failures. This is totally my fault as well, maths fail 101. This makes geom shaders on r600 not fail heavily. Cc: "10.6" "11.0" <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/sb: update last_cf for finalize if.Dave Airlie2015-09-011-0/+3
| | | | | | | | | | | | As Glenn did for finalize_loop we need to update_cf when we add a POP at the end of a shader. I think this fixes one of the earlier shader going off end of memory problems we've stopped. Reviewed-by: Glenn Kennard <[email protected]> Cc: "10.6" "11.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: move prim convert from geom shader to function.Dave Airlie2015-08-312-25/+26
| | | | | | | This should avoid C++ fail including this header. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: Use TGSI parse results instead of manually exfiltratingEdward O'Callaghan2015-08-301-1/+1
| | | | | | | | This makes better use of the work that the TGSI API has done for us. Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* r600g: Set geometry properties in r600_create_shader_state()Edward O'Callaghan2015-08-303-25/+23
| | | | | | | | | | | The selector is shared by all shader variants, so the individual shaders shouldn't change it. Use tgsi_shader_scan() results to set geometry properties within a r600_create_shader_state() call and treat said propertices in the selector as read-only within r600_shader_from_tgsi(). Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* r600g: Move geometry properties state from shader to selectorEdward O'Callaghan2015-08-306-22/+23
| | | | | Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* r600g: Remove dead assigment to 'gs_input_prim' in shader stateEdward O'Callaghan2015-08-302-4/+0
| | | | | | | | Note that 'geometry shader properties' should be carried in the selector state over the shader state in any case. Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: don't use the emit qt keyword in si_init_atomMarek Olšák2015-08-291-2/+2
| | | | It confuses my editor.
* radeonsi: remove no-op 32-bit maskingMarek Olšák2015-08-295-7/+7
| | | | Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: fix the ADDRESS_HI mask for EVENT_WRITE CIK packetsMarek Olšák2015-08-291-8/+8
| | | | | Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]>
* winsys/radeon: handle non-zero finite timeout when waiting for buffersMarek Olšák2015-08-292-38/+41
| | | | Reviewed-by: Alex Deucher <[email protected]>
* freedreno/a3xx: implement half-z clippingIlia Mirkin2015-08-293-2/+4
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: add basic clip plane supportIlia Mirkin2015-08-293-1/+24
| | | | | | | | | The hardware is capable of dealing with GL1-style user clip planes. No clip vertex, no clip distances. Fixes a number of ucp tests, as well as neverball. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0" <[email protected]>
* nvc0: change prefix of MP performance counters to HW_SMSamuel Pitoiset2015-08-292-149/+149
| | | | | | | According to NVIDIA, local performance counters (MP) are prefixed with SM, while global performance counters (PCOUNTER) are called PM. Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: sort performance counter queries by nameSamuel Pitoiset2015-08-292-142/+142
| | | | Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: make names of performance counter queries consistentSamuel Pitoiset2015-08-292-56/+56
| | | | Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: use enumerations for driver queriesSamuel Pitoiset2015-08-291-120/+123
| | | | Signed-off-by: Samuel Pitoiset <[email protected]>
* nvc0: remove commented out code related to PCOUNTER queriesSamuel Pitoiset2015-08-291-20/+0
| | | | Signed-off-by: Samuel Pitoiset <[email protected]>
* r600: port si_conv_prim_to_gs_out from radeonsiDave Airlie2015-08-291-15/+16
| | | | | | | | | This code was broken by the tess merge, and I totally missed it until now. I'm not sure this fixes anything but it stops the assert. Cc: "11.0" <[email protected]> Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g: use PRIi64 for some compute debug printfsDave Airlie2015-08-291-4/+4
| | | | | | | | Otherwise this will crash on 32-bit, and it gets rid of warnings building on 32-bit. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallium/util: fix debug_get_flags_option on 32-bitDave Airlie2015-08-291-3/+4
| | | | | | | | | On 32-bit we need to use PRIu64 flags for printfs, otherwise this segfaults in R600_DEBUG=help otherwise. Reviewed-by: Marek Olšák <[email protected]> Cc: "11.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g/sb: Don't crash on empty if jump targetGlenn Kennard2015-08-281-1/+4
| | | | | | Signed-off-by: Glenn Kennard <[email protected]> Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g/sb: Don't read junk after EOPGlenn Kennard2015-08-283-1/+6
| | | | | | | | | | | | | Shaders that contain instruction data after an instruction with EOP could end up parsing that as an instruction, leading to various crashes and asserts in SB as it gets very confused if it sees for instance a loop start instruction jumping off to some random point. Add a couple of asserts, and print EOP bit if set in old asm printer. Signed-off-by: Glenn Kennard <[email protected]> Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g/sb: Handle undef in read port trackerGlenn Kennard2015-08-281-1/+1
| | | | | | | | | e8e443 missed adding check for undef values also in unreserve function, leading to an assert triggering. Signed-off-by: Glenn Kennard <[email protected]> Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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