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* util/u_blitter: implement alpha blending for pipe->blitMarek Olšák2015-08-217-23/+49
* gallium: Add blending to pipe blitChristoph Bumiller2015-08-213-0/+4
* st/nine: Revert to sw cursor in case of failure to set hw cursorAxel Davy2015-08-211-2/+2
* st/nine: Do not call ID3DPresent_GetCursorPos for sw cursorAxel Davy2015-08-211-3/+4
* st/nine: Force hw cursor for Windowed modeAxel Davy2015-08-211-3/+9
* st/nine: Hide hardware cursor when we don't use itAxel Davy2015-08-211-6/+12
* st/nine: fix D3DRS_DITHERENABLE wrong state groupAxel Davy2015-08-211-1/+1
* st/nine: Account POINTSIZE_MIN and POINTSIZE_MAX for point sizePatrick Rudolph2015-08-213-14/+19
* st/nine: Align texture memoryPatrick Rudolph2015-08-214-6/+6
* st/nine: Always set point_quad_rasterization to 1Axel Davy2015-08-211-1/+1
* st/nine: Fix Swizzle for ATI2 formatAxel Davy2015-08-211-0/+5
* target/d3dadapter9: Return Windows like card namesPatrick Rudolph2015-08-213-42/+359
* clover: fix llvm 3.5 build errorZoltan Gilian2015-08-211-12/+21
* vc4: Add algebraic opt for rcp(1.0).Eric Anholt2015-08-201-0/+8
* vc4: Allow unpack_8[abcd]_f's src to stay in r4.Eric Anholt2015-08-201-1/+15
* vc4: Pack the unorm-packing bits into a src MUL instruction when possible.Eric Anholt2015-08-205-16/+104
* vc4: Add a QIR helper for whether the op is a MUL type.Eric Anholt2015-08-203-4/+16
* vc4: Drop an unused algebraic op.Eric Anholt2015-08-201-9/+0
* vc4: Switch QPU_PACK_SCALED to be two non-SSA instructions.Eric Anholt2015-08-205-21/+19
* vc4: Make the pack-to-unorm instructions be non-SSA.Eric Anholt2015-08-204-42/+36
* vc4: Allow QIR registers to be non-SSA.Eric Anholt2015-08-204-4/+10
* vc4: We can now move TEX_RESULT accesses across other r4 ops.Eric Anholt2015-08-201-16/+0
* nv50/ir: pre-compute BFE arg when both bits and offset are immIlia Mirkin2015-08-201-3/+9
* r600g: Fix handling of TGSI_OPCODE_ARR with SBGlenn Kennard2015-08-211-1/+1
* r600: Turn 'r600_shader_key' struct into unionEdward O'Callaghan2015-08-214-38/+42
* r600: Rewrite r600_shader_selector_key() to use a switch stmtEdward O'Callaghan2015-08-211-7/+17
* nv50/ir: Handle OP_CVT when folding constant expressionsTobias Klausmann2015-08-201-0/+78
* nvc0/ir: undo more shifts still by allowing a pre-SHL to occurIlia Mirkin2015-08-201-15/+33
* nvc0/ir: don't require AND when the high byte is being addressedIlia Mirkin2015-08-201-0/+12
* nvc0/ir: detect i2f/i2i which operate on specific bytes/wordsIlia Mirkin2015-08-204-4/+82
* nvc0/ir: detect AND/SHR pairs and convert into EXTBFIlia Mirkin2015-08-201-20/+46
* nv50/ir: support different unordered_set implementationsChih-Wei Huang2015-08-205-12/+57
* radeonsi: fix a typo as_es -> as_ls in a stringMarek Olšák2015-08-191-1/+1
* winsys/amdgpu: fix the type of memory usage countersMarek Olšák2015-08-191-2/+2
* radeonsi: fix indirect indexing of MSAA texturesMarek Olšák2015-08-191-4/+13
* util/ra: Make allocating conflict lists optionalJason Ekstrand2015-08-183-3/+4
* freedreno: use fd_pipe_wait_timeout()Rob Clark2015-08-182-21/+1
* freedreno: fence fixRob Clark2015-08-183-4/+8
* Add mesa.icd to the .gitignoreNeil Roberts2015-08-181-0/+1
* radeon/uvd: remove unused variablesGrazvydas Ignotas2015-08-181-4/+1
* nouveau: recognize tess stages in nouveau_compilerMarcos Paulo de Souza2015-08-171-0/+4
* tgsi: fix parsing of tessellation shader inputs/outputsMarcos Paulo de Souza2015-08-171-1/+16
* tgsi: set implicit array size for tess stagesMarcos Paulo de Souza2015-08-171-1/+5
* freedreno/a3xx: add s3tc texture format supportIlia Mirkin2015-08-171-0/+9
* freedreno/a3xx: fix up logic for handling block formatsIlia Mirkin2015-08-173-5/+7
* freedreno/a3xx: double the polygon offset valueIlia Mirkin2015-08-171-1/+1
* nvc0: implement the color buffer 0 is integer rule for alpha-to-one/covIlia Mirkin2015-08-173-11/+22
* gk110/ir: fix sched calculator to consider all registers in the ISAIlia Mirkin2015-08-171-7/+10
* nvc0: program smooth line width when multisampling is enabledIlia Mirkin2015-08-171-1/+1
* nvc0: bind a fake tess control program when there isn't one availableIlia Mirkin2015-08-174-8/+44
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