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* draw: fix test for using the wide-point stageBrian Paul2010-09-201-2/+2
| | | | | As it was, we weren't obeying the draw->pipeline.point_sprite state. Fixes point sprites in llvmpipe driver.
* llvmpipe: implement sprite coord origin modesBrian Paul2010-09-201-6/+12
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* llvmpipe: rename sprite field, add sprite_coord_originBrian Paul2010-09-205-6/+10
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* llvmpipe: clean-up, comments in setup_point_coefficient()Brian Paul2010-09-201-5/+10
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* llvmpipe: reformatting, remove trailing whitespace, etcBrian Paul2010-09-201-21/+23
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* llvmpipe: indentation fixBrian Paul2010-09-201-1/+1
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* llvmpipe: maintain fragment shader state for draw moduleBrian Paul2010-09-202-0/+14
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* gallium/docs: added new pipeline.txt diagramBrian Paul2010-09-171-0/+128
| | | | | | This diagram shows the rendering pipeline with an emphasis on the inputs/outputs for each stage. Some stages emit new vertex attributes and others consume some attributes.
* gallium: rework handling of sprite_coord_enable stateBrian Paul2010-09-1710-82/+153
| | | | | | | | | | | | | | | | | | | | Implement the pipe_rasterizer_state::sprite_coord_enable field in the draw module (and softpipe) according to what's specified in the documentation. The draw module can now add any number of extra vertex attributes to a post-transformed vertex and generate texcoords for those attributes per sprite_coord_enable. Auto-generated texcoords for sprites only worked for one texcoord unit before. The frag shader gl_PointCoord input is now implemented like any other generic/texcoord attribute. The draw module now needs to be informed about fragment shaders since we need to look at the fragment shader's inputs to know which ones need auto-generated texcoords. Only softpipe has been updated so far.
* gallium: better docs for pipe_rasterizer_state::sprite_coord_enableBrian Paul2010-09-171-5/+13
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* r600g: alternative command stream building from contextJerome Glisse2010-09-1714-25/+5913
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Winsys context build a list of register block a register block is a set of consecutive register that will be emited together in the same pm4 packet (the various r600_block* are there to provide basic grouping that try to take advantage of states that are linked together) Some consecutive register are emited each in a different block, for instance the various cb[0-7]_base. At winsys context creation, the list of block is created & an index into the list of block. So to find into which block a register is in you simply use the register offset and lookup the block index. Block are grouped together into group which are the various pkt3 group of config, context, resource, Pipe state build a list of register each state want to modify, beside register value it also give a register mask so only subpart of a register can be updated by a given pipe state (the oring is in the winsys) There is no prebuild register list or define for each pipe state. Once pipe state are built they are bound to the winsys context. Each of this functions will go through the list of register and will find into which block each reg falls and will update the value of the block with proper masking (vs/ps resource/constant are specialized variant with somewhat limited capabilities). Each block modified by r600_context_pipe_state_set* is marked as dirty and we update a count of dwords needed to emit all dirty state so far. r600_context_pipe_state_set* should be call only when pipe context change some of the state (thus when pipe bind state or set state) Then to draw primitive you make a call to r600_context_draw void r600_context_draw(struct r600_context *ctx, struct r600_draw *draw) It will check if there is enough dwords in current cs buffer and if not will flush. Once there is enough room it will copy packet from dirty block and then add the draw packet3 to initiate the draw. The flush will send the current cs, reset the count of dwords to 0 and remark all states that are enabled as dirty and recompute the number of dwords needed to send the current context. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: Fixed the shift in S_02880C_KILL_ENABLE.Tilman Sauerbeck2010-09-172-2/+2
| | | | Signed-off-by: Tilman Sauerbeck <[email protected]>
* r600g: Enable PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED.Tilman Sauerbeck2010-09-171-2/+1
| | | | Signed-off-by: Tilman Sauerbeck <[email protected]>
* r600g: Only set PA_SC_EDGERULE on rv770 and greater.Tilman Sauerbeck2010-09-171-2/+14
| | | | | | This is what xf86-video-ati and r600c do. Signed-off-by: Tilman Sauerbeck <[email protected]>
* r600g: Added DB_SHADER_CONTROL defines.Tilman Sauerbeck2010-09-174-6/+46
| | | | Signed-off-by: Tilman Sauerbeck <[email protected]>
* r600g: Formatting fixes.Tilman Sauerbeck2010-09-171-27/+26
| | | | Signed-off-by: Tilman Sauerbeck <[email protected]>
* r600g: oops got the use_mem_constant the wrong way around.Dave Airlie2010-09-181-1/+1
| | | | this fixes evergreen gears again.
* r600g: use calloc for ctx bo allocationsDave Airlie2010-09-171-1/+1
| | | | since the reference code relies on these being NULL.
* r600g: fixup map flushing.Dave Airlie2010-09-171-5/+9
| | | | | | long lived maps were getting removed when they shouldn't this tries to avoid that problem by only adding to the flush list on unmap.
* r600g: add upload manager support.Dave Airlie2010-09-176-47/+223
| | | | | | this add support for the upload manager for uploading user vbo/index buffers. this provides a considerable speedup in q3 type games.
* r600g: add winsys bo caching.Dave Airlie2010-09-174-31/+24
| | | | | | | this adds the bo caching layer and uses it for vertex/index/constant bos. ctx needs to take references on hw bos so the flushing works okay, also needs to flush the maps.
* r600g: add support for kernel boDave Airlie2010-09-1710-50/+352
| | | | this moves to using a pb bufmgr instead of kernel bos directly.
* r600g: use malloc bufmgr for constant buffersDave Airlie2010-09-173-1/+9
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* r600g: move constant buffer creation behind winsys abstraction.Dave Airlie2010-09-1712-55/+65
| | | | this paves the way for moving to pb bufmgrs now.
* libgl-xlib: Remove unused st_api_create_OpenGL.Chia-I Wu2010-09-171-8/+0
| | | | st/egl no longer relies on libGL for OpenGL support.
* targets/egl: Use C++ compiler to link GL/ES state trackers.Chia-I Wu2010-09-171-3/+10
| | | | | Otherwise, applications compiled with C compiler might have trouble using them.
* tgsi/sse: fix aos_to_soa() loop to handle num_inputs==0Brian Paul2010-09-161-6/+9
| | | | | | | | | Basically, change the loop from: do {...} while (--num_inputs != 0) into: while (num_inputs != 0) { ... --num_inputs; } Fixes fd.o bug 29987.
* r600g: attempt to abstract kernel bos from pipe driver.Dave Airlie2010-09-1719-199/+272
| | | | | | introduce an abstraction layer between kernel bos and the winsys BOs. this is to allow plugging in pb manager with minimal disruption to pipe driver.
* r600g: hide radeon_ctx inside winsys.Dave Airlie2010-09-178-56/+42
| | | | no need for this info to be exported to pipe driver.
* gallivm: Remove unnecessary header.Vinson Lee2010-09-161-1/+0
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* gallivm: fix wrong return value in bitwise functionsBrian Paul2010-09-161-3/+3
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* gallivm: Clamp indirect register indices to file_max.José Fonseca2010-09-161-60/+71
| | | | Prevents crashes with bogus data, or bad shader translation.
* gallivm: Start collecting bitwise arithmetic helpers in a new module.José Fonseca2010-09-168-32/+263
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* gallivm: Fix address register swizzle.José Fonseca2010-09-161-2/+1
| | | | | | | | | | We're actually doing a double swizzling: indirect_reg->Swizzle[indirect_reg->SwizzleX] instead of simply indirect_reg->SwizzleX
* r300g/swtcl: fix CS overrunMarek Olšák2010-09-162-8/+28
| | | | https://bugs.freedesktop.org/show_bug.cgi?id=29901
* llvmpipe: add DEBUG_FS to dump variant informationKeith Whitwell2010-09-163-1/+3
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* llvmpipe: add LP_PERF flag to disable various aspects of rasterizationKeith Whitwell2010-09-168-6/+90
| | | | | | | | Allows disabling various operations (mainly texture-related, but will grow) to try & identify bottlenecks. Unlike LP_DEBUG, this is active even in release builds - which is necessary for performance investigation.
* gallivm: make lp_build_sample_nop publicKeith Whitwell2010-09-162-6/+8
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* gallivm: move i32_vec_type inside the #ifdefBrian Paul2010-09-161-1/+2
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* gallivm: fix incorrect vector shuffle datatypeBrian Paul2010-09-161-1/+5
| | | | The permutation vector must always be a vector of int32 values.
* nv50: get shader fixups/relocations into working stateChristoph Bumiller2010-09-164-54/+79
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* nv50: don't segfault on shaders with 0 instructionsChristoph Bumiller2010-09-161-1/+3
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* r600g: Use clamped math for RCP and RSQ.Tilman Sauerbeck2010-09-161-2/+14
| | | | | | This is likely only correct for OpenGL and not other state trackers. Signed-off-by: Tilman Sauerbeck <[email protected]>
* r600g: Fixed a bo leak in r600_blit_state_ps_shader().Tilman Sauerbeck2010-09-161-1/+1
| | | | | | We would leak the newly created bo if it cannot be mapped. Signed-off-by: Tilman Sauerbeck <[email protected]>
* st/xlib: Notify the context when the front/back buffers are swapped.Chia-I Wu2010-09-163-4/+21
| | | | | | | | The current context should be notified when the the front/back buffers of the current drawable are swapped. The notification was skipped when xmesa_strict_invalidate is false (the default). This fixes fdo bug #29774.
* r600g: fix texture bos and avoid doing depth blit on evergreenDave Airlie2010-09-162-11/+4
| | | | since the depth blit code is hardcoded hex yay \o/
* r600g: fixup texture state on evergreen.Dave Airlie2010-09-164-143/+317
| | | | This whole set of state just seems wrong, another cut-n-paste nightmare.
* nv50: Fix 'control reaches end of non-void function' warning.Vinson Lee2010-09-151-0/+1
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* nv50: Silence uninitialized variable warnings.Vinson Lee2010-09-151-1/+2
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* draw: Remove unnecessary header.Vinson Lee2010-09-151-1/+0
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