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* winsys/amdgpu: move gart_page_size to struct radeon_winsysMarek Olšák2016-05-104-10/+10
* gallivm: print declarations of intrinsics with GALLIVM_DEBUG=irRoland Scheidegger2016-05-101-0/+5
* gallivm: use InternalLinkage instead of PrivateLinkage for texture functionsRoland Scheidegger2016-05-101-1/+1
* gallivm: disable avx512 featuresRoland Scheidegger2016-05-101-0/+12
* freedreno/ir3: lower lrp when operating with double operandsSamuel Iglesias Gonsálvez2016-05-101-0/+1
* nv50/ir: silence unsupported TGSI_PROPERTY_CS_FIXED_BLOCK_*Samuel Pitoiset2016-05-091-0/+5
* freedreno/ir3: fix fallout from new block iteratorsRob Clark2016-05-091-1/+1
* radeonsi: workaround for tesselation on SINicolai Hähnle2016-05-091-0/+8
* radeonsi: always allocate export memory for pixel shadersNicolai Hähnle2016-05-091-5/+10
* radeonsi: expose performance counters as 64 bitNicolai Hähnle2016-05-092-16/+19
* gallium: enable intel jitevents profilingTim Rowley2016-05-091-0/+9
* swr: Add missing break in query switch statement.Bruce Cherniak2016-05-091-0/+1
* freedreno/ir3: allow for additional VS sysval inputsRob Clark2016-05-091-2/+5
* r300g: add support for PIPE_FORMAT_x8R8G8B8_*Marek Olšák2016-05-092-15/+77
* radeonsi: fix undefined behavior (memcpy arguments must be non-NULL)Nicolai Hähnle2016-05-071-1/+3
* radeonsi: fix some reported undefined left-shiftsNicolai Hähnle2016-05-071-3/+3
* gallium/radeon: clean left-shift undefined behaviorNicolai Hähnle2016-05-0711-3989/+3989
* gallium: fix various undefined left shifts into sign bitNicolai Hähnle2016-05-074-5/+5
* radeonsi: Compute correct LDS size for fragment shaders.Bas Nieuwenhuizen2016-05-061-3/+6
* vc4: Add support for loading immediate values in QIR.Eric Anholt2016-05-064-0/+32
* vc4: Make vc4_qpu_validate() produce more verbose failures.Eric Anholt2016-05-061-35/+71
* vc4: Add a small QIR validate pass.Eric Anholt2016-05-064-0/+127
* vc4: Fix the src count on exp2/log2.Eric Anholt2016-05-061-2/+2
* vc4: Reuse QPU disasm's cond flags in QIR.Eric Anholt2016-05-063-27/+46
* vc4: When emitting an instruction to an existing temp, mark it non-SSA.Eric Anholt2016-05-061-0/+2
* vc4: Make sure that we don't overwrite the signal for PROG_END.Eric Anholt2016-05-061-0/+8
* nvc0: unreference images when the context is destroyedSamuel Pitoiset2016-05-061-0/+4
* radeonsi: set DECOMPRESS_Z_ON_FLUSH if nr_samples >= 4Marek Olšák2016-05-061-1/+2
* r600g: use the hw MSAA resolving if formats are compatibleMarek Olšák2016-05-061-1/+2
* st/omx/enc: fix incorrect reference picture order for B framesLeo Liu2016-05-051-7/+12
* vc4: fixup for new nir_foreach_block()Connor Abbott2016-05-054-48/+20
* ir3: fixup for new nir_foreach_block()Connor Abbott2016-05-051-30/+21
* swr: [rasterizer core] Faster modulo operator in ProcessVertsTim Rowley2016-05-051-1/+4
* swr: [rasterizer] Small warning cleanupTim Rowley2016-05-052-8/+4
* swr: [rasterizer] Add SWR_ASSUME / SWR_ASSUME_ASSERT macrosTim Rowley2016-05-052-14/+52
* swr: [rasterizer] Miscellaneous backend changesTim Rowley2016-05-053-22/+31
* swr: [rasterizer] Add support for X24_TYPELESS_G8_UINT formatTim Rowley2016-05-053-7/+41
* swr: [rasterizer jitter] Fix printing bugs for tracing.Tim Rowley2016-05-051-81/+24
* swr: [rasterizer memory] Add missing store tiles functionTim Rowley2016-05-051-1/+4
* swr: [rasterizer jitter] Add asserts for supported formats in fetch shaderTim Rowley2016-05-051-0/+2
* swr: [rasterizer core] Fix thread allocationTim Rowley2016-05-051-17/+47
* swr: [rasterizer core] Fix threadviz support in bucketsTim Rowley2016-05-053-12/+14
* swr: [rasterizer] Whitespace cleanup and misc changesTim Rowley2016-05-055-5/+2
* radeonsi: mark descriptor loads as using dynamically uniform indicesNicolai Hähnle2016-05-051-5/+17
* swr: Remove stall waiting for core query counters.Bruce Cherniak2016-05-054-124/+81
* freedreno: remove null check before freeThomas Hindoe Paaboel Andersen2016-05-051-2/+1
* r600,compute: create vtx buffer for text + rodataJan Vesely2016-05-041-2/+10
* freedreno: allow ctx->draw_vbo to failRob Clark2016-05-045-30/+37
* freedreno: move shader-stage dirty bits to global dirty flagRob Clark2016-05-048-59/+41
* freedreno/a4xx: fix bogus offset for f32x24s8 stencil restoreRob Clark2016-05-041-4/+5
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