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* util: add trivial comment on u_upload_create()Brian Paul2017-12-261-0/+1
* r600: fix atomic counter index mode getting emitted on pre-caymanDave Airlie2017-12-271-1/+1
* radv/radeonsi: set dcc min uncompressed properly for APUs.Dave Airlie2017-12-271-0/+9
* amd/common/radv/radeonsi: use register defines for dcc block sizes.Dave Airlie2017-12-271-3/+3
* radeonsi: don't use fast color clear for small images even on APUsMarek Olšák2017-12-251-5/+4
* radeonsi: set PNT_SPRITE_ENA = point_quad_rasterizationMarek Olšák2017-12-251-1/+1
* gallium/util: add util_num_layers helperMarek Olšák2017-12-257-15/+21
* freedreno: set missing internal_format when importing textureIlia Mirkin2017-12-221-0/+1
* amd/common: add ac_export_mrt_z() helperSamuel Pitoiset2017-12-221-60/+1
* amd/common: pass the family to ac_llvm_context_init()Samuel Pitoiset2017-12-221-1/+2
* gm107/ir: use lane 0 for manual textureGrad handlingIlia Mirkin2017-12-221-21/+34
* st/dri: allow direct YUYV importLucas Stach2017-12-201-0/+7
* nvc0/ir: change textureGrad to always use lane 0 as the tex originIlia Mirkin2017-12-191-14/+46
* broadcom/vc5: Add missing setting of the UIF XOR disable flag in textures.Eric Anholt2017-12-191-0/+3
* broadcom/vc5: Clean up the comment and code around level 0 UIF.Eric Anholt2017-12-191-14/+10
* broadcom/vc5: Simplify the tiling calculations.Eric Anholt2017-12-191-49/+11
* broadcom/vc5: Return the depth in all components of depth textures.Eric Anholt2017-12-191-6/+6
* broadcom/vc5: Enable decompressing RGTC for desktop GL support.Eric Anholt2017-12-191-1/+1
* broadcom/vc5: Use u_transfer_helper for MSAA mappings.Eric Anholt2017-12-192-98/+6
* broadcom/vc5: Start adding support for rendering to Z32F_S8X24_UINT.Eric Anholt2017-12-193-5/+94
* freedreno: add debug flag to force high priority contextRob Clark2017-12-193-1/+5
* freedreno: context priority supportRob Clark2017-12-193-2/+20
* gallium: plumb context priority through to driverRob Clark2017-12-1921-2/+66
* freedreno/ir3: handle VTXID_BASE for indirect drawsRob Clark2017-12-191-2/+41
* freedreno/ir3: add ctx->mem_to_mem()Rob Clark2017-12-194-14/+49
* freedreno/a5xx: use vertex_id_zero_baseRob Clark2017-12-192-20/+1
* r600: clear compressed flags in image state on unbind.Dave Airlie2017-12-191-0/+2
* swr: Account for index_bias in offsetsGeorge Kyriazis2017-12-181-3/+3
* r600: only reported tgsi ir compute support on evergreen+Dave Airlie2017-12-181-1/+3
* amd/common: add ac_vgt_gs_mode() helperSamuel Pitoiset2017-12-181-29/+3
* amd/common: add ac_get_cb_shader_mask() helperSamuel Pitoiset2017-12-181-33/+1
* r600: export robust buffer accessDave Airlie2017-12-181-1/+1
* r600: export GLSL 430Dave Airlie2017-12-181-1/+1
* r600/cs: add compute support to capsDave Airlie2017-12-181-2/+2
* r600: always flush between gfx and computeDave Airlie2017-12-185-0/+21
* r600: fix unused variable warningDave Airlie2017-12-181-1/+0
* freedreno/a5xx: add a5xx blitterRob Clark2017-12-178-1/+498
* freedreno: add generic blitterRob Clark2017-12-177-2/+161
* freedreno: add non-draw batches for compute/blitRob Clark2017-12-1712-32/+82
* freedreno: track staging and shadow perf ctrs for the HUDRob Clark2017-12-175-0/+16
* freedreno: staging upload transfersRob Clark2017-12-173-43/+135
* freedreno: update generated headersRob Clark2017-12-177-63/+334
* radeonsi: don't call force_dcc_off for buffersMarek Olšák2017-12-161-1/+1
* radeon/uvd: add and manage render picture listBoyuan Zhang2017-12-151-4/+25
* radeon/vcn: add and manage render picture listBoyuan Zhang2017-12-151-4/+24
* vl: remove is idr flagBoyuan Zhang2017-12-151-1/+0
* st/va: directly use idr pic flagBoyuan Zhang2017-12-151-5/+3
* radeon/vce: determine idr by pic typeBoyuan Zhang2017-12-151-1/+1
* radeon/vcn: determine idr by pic typeBoyuan Zhang2017-12-151-1/+1
* swr/rast: Move more RTAI handling out of binnerTim Rowley2017-12-152-12/+2
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