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* st/nine: Bind src not dst in nine_context_box_uploadAxel Davy2018-12-234-6/+6
* st/nine: Fix volumetexture dtor on ctor failureAxel Davy2018-12-231-1/+2
* st/nine: Switch to presentation buffer if resize is detectedAxel Davy2018-12-231-1/+36
* st/nine: Use helper to release swapchain buffers laterAxel Davy2018-12-232-8/+42
* freedreno/a6xx: fix 3d texture layoutRob Clark2018-12-223-3/+15
* freedreno: update generated headersRob Clark2018-12-227-21/+28
* freedreno/a6xx: improve setup_slices() debug msgsRob Clark2018-12-221-6/+5
* freedreno/a6xx: simplify special case for 3d layoutRob Clark2018-12-221-9/+10
* freedreno: combine fd_resource_layer_offset()/fd_resource_offset()Rob Clark2018-12-221-13/+2
* gallivm: abort when trying to use non-existing intrinsicRoland Scheidegger2018-12-211-0/+10
* gallivm: don't use pavg.b intrinsic on llvm >= 6.0Roland Scheidegger2018-12-212-51/+95
* pipe-loader: meson: reference correct libraryEmil Velikov2018-12-131-1/+1
* vc4: Hook up perf_debug() output to GL_ARB_debug_output as well.Eric Anholt2018-12-202-0/+3
* vc4: Wire up core pipe_debug_callbackRhys Kidd2018-12-202-0/+14
* v3d: Hook up perf_debug() output to GL_ARB_debug output as well.Eric Anholt2018-12-202-0/+3
* v3d: Wire up core pipe_debug_callbackRhys Kidd2018-12-202-0/+14
* v3d: Drop shadow comparison state from shader variant key.Eric Anholt2018-12-201-2/+0
* v3d: Fix simulator mode on i915 render nodes.Eric Anholt2018-12-201-28/+73
* gallivm: use llvm jit code for decoding s3tcRoland Scheidegger2018-12-207-383/+2239
* v3d: Load and store aligned utiles all at once.Eric Anholt2018-12-191-8/+114
* vc4: Move the utile load/store functions to a header for reuse by v3d.Eric Anholt2018-12-192-202/+11
* v3d: Implement texture_subdata to reduce teximage upload copies.Eric Anholt2018-12-191-29/+85
* v3d: Remove dead prototypes for load/store utile functions.Eric Anholt2018-12-191-2/+0
* v3d: Don't try to create shadow tiled temporaries for 1D textures.Eric Anholt2018-12-191-1/+2
* v3d: Fix check for TFU job completion in the simulator.Eric Anholt2018-12-191-1/+1
* v3d: Put the dst bo first in the list of BOs for TFU calls.Eric Anholt2018-12-191-2/+2
* winsys/amdgpu: Pull in LLVM CFLAGSMichel Dänzer2018-12-192-1/+2
* virgl: move resource creation / import / destruction to common codeGurchetan Singh2018-12-194-114/+89
* virgl: move resource metadata into base resourceGurchetan Singh2018-12-194-91/+71
* virgl: modify how we handle GL_MAP_FLUSH_EXPLICIT_BITGurchetan Singh2018-12-194-69/+25
* virgl: make virgl_buffers use resource helpersGurchetan Singh2018-12-192-20/+11
* virgl: make transfer code with PIPE_BUFFER targetsGurchetan Singh2018-12-191-2/+4
* virgl: consolidate transfer codeGurchetan Singh2018-12-195-59/+73
* virgl: store layer_stride in metadataGurchetan Singh2018-12-192-6/+6
* virgl: move vrend_get_tex_image_offset to common codeGurchetan Singh2018-12-193-26/+28
* virgl: move virgl_resource_layout to common codeGurchetan Singh2018-12-193-42/+51
* virgl: move texture metadata to common codeGurchetan Singh2018-12-192-12/+18
* virgl: remove unnessecary codeGurchetan Singh2018-12-191-3/+0
* virgl: texture_transfer_pool --> transfer_poolGurchetan Singh2018-12-196-11/+11
* radeonsi: const-ify the si_query_opsNicolai Hähnle2018-12-193-5/+5
* radeonsi: split perfcounter queries from si_query_hwNicolai Hähnle2018-12-191-50/+93
* radeonsi: factor si_query_buffer logic out of si_query_hwNicolai Hähnle2018-12-194-110/+99
* radeonsi: move query suspend logic into the top-level si_query structNicolai Hähnle2018-12-193-44/+62
* radeonsi: move remaining perfcounter code into si_perfcounter.cNicolai Hähnle2018-12-197-766/+643
* radeonsi: track constant buffer bind history in si_pipe_set_constant_bufferNicolai Hähnle2018-12-191-2/+3
* radeonsi: use si_set_rw_shader_buffer for setting streamout buffersNicolai Hähnle2018-12-191-50/+11
* radeonsi: add an si_set_rw_shader_buffer convenience functionNicolai Hähnle2018-12-192-45/+64
* radeonsi: avoid using hard-coded SI_NUM_RW_BUFFERSNicolai Hähnle2018-12-191-1/+2
* radeonsi: show the fixed function TCS in debug dumpsNicolai Hähnle2018-12-191-2/+8
* radeonsi: const-ify si_set_tesseval_regsNicolai Hähnle2018-12-191-2/+2
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