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* radeonsi: use compute shaders for clear_buffer & copy_bufferMarek Olšák2018-10-168-203/+350
* radeonsi: use copy_buffer in buffer_do_flush_region directlyMarek Olšák2018-10-161-11/+4
* radeonsi: use faster integer division for instance divisorsMarek Olšák2018-10-163-36/+83
* radeonsi: use higher subpixel precision (QUANT_MODE) for smaller viewportsMarek Olšák2018-10-163-9/+53
* radeonsi: move emission of PA_SU_VTX_CNTL into emit_guardbandMarek Olšák2018-10-164-6/+11
* radeonsi: don't re-upload the sample position constant buffer repeatedlyMarek Olšák2018-10-164-16/+33
* radeonsi: set PA_SU_PRIM_FILTER_CNTL optimallyMarek Olšák2018-10-163-4/+13
* radeonsi: center viewport to improve guardband clipping for high resolutionsMarek Olšák2018-10-164-14/+62
* radeonsi: save raster config in screen, add se_tile_repeatMarek Olšák2018-10-163-7/+17
* radeonsi: switch back to standard DX sample positionsMarek Olšák2018-10-161-17/+26
* radeonsi: add GDS support to CP DMAMarek Olšák2018-10-163-21/+89
* radeonsi: rename si_gfx_* functions to si_cp_*Marek Olšák2018-10-165-59/+59
* radeonsi: make si_gfx_write_event_eop more configurableMarek Olšák2018-10-165-15/+29
* intel/nir, freedreno/ir3: Use the separated dead write vars passCaio Marcelo de Oliveira Filho2018-10-151-0/+1
* v3d: Add support for hardware pack/unpack of half floats.Eric Anholt2018-10-151-0/+1
* gallium/ttn: Convert inputs and outputs to derefs of variables.Eric Anholt2018-10-154-69/+64
* gallium/ttn: Fix the type of gl_FragDepth.Eric Anholt2018-10-151-0/+1
* freedreno/a6xx: Enable blitterKristian H. Kristensen2018-10-155-0/+623
* freedreno/a6xx: Update headersKristian H. Kristensen2018-10-151-16/+30
* freedreno/a6xx: Remove unnecessary GRAS_2D_BLIT_INFO writeKristian H. Kristensen2018-10-151-2/+0
* gallium/u_transfer_helper: Add support for separate Z24/S8 as well.Kenneth Graunke2018-10-145-22/+60
* gallium/format: Add a helper to combine separate Z24 and S8 stencil.Kenneth Graunke2018-10-142-0/+22
* gallium/auxiliary: Add util_format_get_depth_only() helper.Kenneth Graunke2018-10-141-0/+21
* r600/sb: Fix constant-logical-operand warning.Vinson Lee2018-10-121-1/+1
* scons: Allow building with custom MSVC_USE_SCRIPT script.Jose Fonseca2018-10-121-0/+1
* st/va: use provided sizes and coords for vlVaGetImageBoyuan Zhang2018-10-111-3/+28
* svga: change svga_destroy_shader_variant() to return voidBrian Paul2018-10-095-23/+6
* nvc0: fix blitting red to srgb8_alphaIlia Mirkin2018-10-091-0/+4
* nv50,nvc0: guard against zero-size blitsIlia Mirkin2018-10-092-0/+14
* nv50,nvc0: mark RGBX_UINT formats as renderableIlia Mirkin2018-10-091-4/+4
* st/dri: Handle BGRA5551 formatMichel Dänzer2018-10-091-0/+13
* freedreno/a5xx+a6xx: fix LRZ pitch alignmentRob Clark2018-10-081-1/+1
* freedreno/a6xx: add LRZ supportRob Clark2018-10-088-132/+104
* freedreno: update generated headersRob Clark2018-10-087-38/+120
* freedreno/a6xx: add helper for various CP_EVENT_WRITERob Clark2018-10-085-38/+30
* freedreno/a6xx: remove unused fxnsRob Clark2018-10-082-19/+0
* freedreno/a6xx: remove fd6_shader_stateobjRob Clark2018-10-083-23/+10
* util/u_queue: add UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITYMarek Olšák2018-10-061-1/+3
* radeonsi: fix a typo at CS_PARTIAL_FLUSHMarek Olšák2018-10-061-1/+1
* ac: add ac_build_roundMarek Olšák2018-10-061-3/+1
* ac: correct PKT3_COPY_DATA definitionsMarek Olšák2018-10-064-6/+6
* ac: define all address spaces properlyMarek Olšák2018-10-061-3/+3
* gallivm: Make it possible to disable some optimization shortcuts in release b...Gert Wollny2018-10-064-21/+32
* virgl: Pass resource size and transfer offsetsTomeu Vizoso2018-10-064-28/+208
* virgl, vtest: Correct the transfer size calculationGert Wollny2018-10-061-1/+3
* radeonsi:optimizing SET_CONTEXT_REG for shaders vgt_vertex_reuseSonny Jiang2018-10-054-2/+18
* radeonsi:optimizing SET_CONTEXT_REG for shaders TessellationSonny Jiang2018-10-054-5/+26
* radeonsi:optimizing SET_CONTEXT_REG for shaders PSSonny Jiang2018-10-053-14/+60
* radeonsi:optimizing SET_CONTEXT_REG for shaders VSSonny Jiang2018-10-053-33/+77
* radeonsi:optimizing SET_CONTEXT_REG for shaders GSSonny Jiang2018-10-054-24/+154
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