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* broadcom/vc5: Move stencil state packing to the CSO.Eric Anholt2017-11-073-27/+47
| | | | Only the stencil ref comes in as dynamic state at emit time.
* broadcom/vc5: Introduce a helper for pre-packing our V3DXX structs.Eric Anholt2017-11-072-165/+155
| | | | | | This is so much more pleasant to write than the manual V3D33_whatever_pack() calls, and will be useful for when we start doing actual per-V3D compiles.
* broadcom/vc5: Add a cl_emit() variant for merging with a pre-packed struct.Eric Anholt2017-11-072-19/+29
| | | | Cleans up the hand-written code, at the cost of another ugly macro.
* broadcom/vc5: Skip emitting depth offset while disabled.Eric Anholt2017-11-071-1/+4
| | | | | The enable flag is also in the rasterizer state, so it will be emitted once it's needed.
* broadcom/vc5: Don't emit stencil config if not doing stencil test.Eric Anholt2017-11-071-1/+2
| | | | | | As with blending, we'll have the bit flagged again when it gets reenabled in CONFIGURATION_BITS, so there's no need to emit test state if we're not testing.
* broadcom/vc5: Don't emit updated blend factors/funcs while disabled.Eric Anholt2017-11-071-1/+5
| | | | | The dirty bit will be flagged again when re-enbaled. Keeps us from emitting blend state in CLs that never do blending.
* broadcom/vc5: Make sure the TMU indirect struct is appropriately aligned.Eric Anholt2017-11-071-0/+2
| | | | | I was hoping that this would help with fbo-generatemipmap hangs, but no luck.
* broadcom/vc5: Use DEPTH24_STENCIL8 for rendering to depth-only textures.Eric Anholt2017-11-071-1/+1
| | | | | | | | | The HW puts the pad bits at the top for DEPTH_COMPONENT24, but we need it at the bottom for texturing. Using the format with stencil probably means we won't be able to do Z24 and separate S8, but I wasn't planning on supporting that anyway. Fixes hiz-depth-read-fbo-d24-s0
* radeonsi: add si_screen::has_ls_vgpr_init_bugMarek Olšák2017-11-074-3/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use ac_create_target_machineMarek Olšák2017-11-071-15/+7
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use ac_get_llvm_processor_nameMarek Olšák2017-11-073-38/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: don't set gs_table_depthMarek Olšák2017-11-071-2/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: limit the scissor bug workaround to Vega10 and Raven onlyMarek Olšák2017-11-071-4/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove unused field in the PCI ID tableMarek Olšák2017-11-071-1/+1
| | | | Reviewed-by: Alex Deucher <[email protected]>
* gallium: Guard assertions by NDEBUG instead of DEBUGMichel Dänzer2017-11-071-1/+1
| | | | | | | This matches the standard assert.h header. Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* meson: standardize .so version to major.minor.patchEric Engestrom2017-11-071-1/+1
| | | | | | | | | | | | | | This `version` field defines the filename for the .so. The plan .so as well as .so.$major are always symlinks to this. Unless I'm mistaken, only the major is ever used, so this shouldn't matter, but for consistency with autotools (and in case it does matter), let's always have all 3 major.minor.patch components. (The soname isn't affected, and is always .so.$major) Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* drisw: Enable flush control for llvmpipe and softpipeAdam Jackson2017-11-061-0/+1
| | | | | | | | | | | | | | | | Hilariously this is a fairly big win. Neil's multi-context-test improves from ~24 to ~36 fps with llvmpipe on a Core i5-3317U. softpipe also improves, from about 2.25 to 3.09 fps (when it's that slow, you're allowed to be that precise). I'd have added it to swrast classic, but the testcase wants GL 3.0 and shaders, and that's not a thing classic has, so I figured making it work on softpipe was crime enough. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* gallium: Wire up flush controlAdam Jackson2017-11-062-1/+6
| | | | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Adam Jackson <[email protected]>
* dri: Change __DriverApiRec::CreateContext to take a struct for attribsNeil Roberts2017-11-062-28/+24
| | | | | | | | | | | | | | | | | | | | Previously the CreateContext method of __DriverApiRec took a set of arguments to describe the attribute values from the window system API's CreateContextAttribs function. As more attributes get added this could quickly get unworkable and every new attribute needs a modification for every driver. To fix that, pass the attribute values in a struct instead. The struct has a bitmask to specify which members are used. The first three members (two for the GL version and one for the flags) are always set. If the bit is not set in the attribute mask then it can be assumed the attribute has the default value. Drivers will error if unknown bits in the mask are set. Reviewed-by: Adam Jackson <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Neil Roberts <[email protected]>
* etnaviv: Don't over-pad compressed texturesWladimir J. van der Laan2017-11-061-9/+15
| | | | | | | | | HALIGN_FOUR/SIXTEEN has no meaning for compressed textures, and we can't render to them anyway. So use the tightest possible packing. This avoids bugs with non-power-of-two block sizes. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: ASTC texture supportWladimir J. van der Laan2017-11-067-2/+57
| | | | | | | | Add ASTC texture support for hardware that supports this (currently only GC3000 on i.MX6qp is known to have this). Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: Update from rnndbWladimir J. van der Laan2017-11-0613-320/+1015
| | | | | | | Updated as of etnav_viv commit 3b4a8ec. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* gallium/u_vbuf: use signed vertex buffers offsets for optimal uploadsMarek Olšák2017-11-061-2/+10
| | | | | | | | | | | | | | | Uploaded data must start at (stride * start), because we can't modify start in all cases. If it's the first allocation, it's also the amount of memory wasted. If the starting offset is larger than the size of the upload buffer, the buffer is re-created, used for 1 upload, and then thrown away. If the upload is small, most of the buffer space is unused and wasted. Keep doing that and the OOM killer comes. It's actually pretty quick. With signed VB offsets, we can set min_out_offset = 0 in u_upload_alloc/u_upload_data. This fixes OOM situations with SPECviewperf.
* radeonsi: enable signed vertex buffer offsetsMarek Olšák2017-11-062-15/+12
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* gallium: add PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSETMarek Olšák2017-11-0618-0/+21
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* radeonsi: don't map big VRAM buffers for the first upload directlyMarek Olšák2017-11-062-0/+21
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/u_threaded: don't map big VRAM buffers for the first upload directlyMarek Olšák2017-11-063-2/+28
| | | | | | | This improves Paraview "many spheres" performance 4x along with the radeonsi commit. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/u_threaded: clean up tc_improve_map_buffer_flags and prevent reentryMarek Olšák2017-11-061-7/+12
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* nv50,nvc0: Display shared memory usage in pipe_debug_messagePierre Moreau2017-11-042-6/+8
| | | | Signed-off-by: Pierre Moreau <[email protected]>
* nv50,nvc0: Copy shared memory per block to the program info structure and backPierre Moreau2017-11-042-0/+4
| | | | | | | | In OpenCL/CUDA kernels, shared memory usage can be defined within the kernel code. Those usage will only be picked up while parsing the SPIR-V, during the translation phase of the program. Signed-off-by: Pierre Moreau <[email protected]>
* nv50/ir: Store shared memory per block in nv50_ir_prog_infoPierre Moreau2017-11-041-0/+1
| | | | Signed-off-by: Pierre Moreau <[email protected]>
* winsys/amdgpu: Add R600_DEBUG flag to reserve VMID per ctx.Andrey Grodzovsky2017-11-034-0/+15
| | | | | | | | | | Fixes reverted patch f03b7c9 by doing VMID reservation per process and not per context. Also updates required amdgpu libdrm version since the change involved interface updates in amdgpu libdrm. Signed-off-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* i915g: remove some unknown cap warnings.Dave Airlie2017-11-031-0/+8
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* i915g: make gears run again.Dave Airlie2017-11-034-4/+24
| | | | | | | We need to validate some structs exist before we dirty the states, and avoid the problem in some other places. Fixes: e027935a7 ("st/mesa: don't update unrelated states in non-draw calls such as Clear")
* ac/radeonsi: add support for tex instr without a derefenceTimothy Arceri2017-11-031-0/+5
| | | | | | | | | | | These are produced by nir_lower_bitmap(), adding the missing derefence would cause other issues that need to be hacked around such as skipping sampler lowering and uniform location assignment, so this change seems the correct way to go. Fixes 194 piglit crashes on radeonsi using NIR. Reviewed-by: Nicolai Hähnle <[email protected]>
* r600: add support for early depth/stencil.Dave Airlie2017-11-031-0/+3
| | | | | | | | This add support for the early depth/stencil property found on image shaders. Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: add support for emitting RAT instructions to the assembler.Dave Airlie2017-11-033-0/+35
| | | | | | | | This adds support for emitting RAT instructions to the assembler. RAT instructions are used to implement image accessors. Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: add support for mark bit to the assembler.Dave Airlie2017-11-033-0/+7
| | | | | | | | This adds support to the assembler for the mark bit on the export word1. Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: add support for valid pixel mode on CF clausesDave Airlie2017-11-032-0/+2
| | | | | | | | This just adds support to the assembler for setting the valid pixel mode on the CF clause. Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: add support for some ALU sources.Dave Airlie2017-11-031-0/+9
| | | | | | | | | | These special ALU sources provide the shader engine, simd and hw wave ids. These are required for images support. Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: remove 'Authors:' commentsMarek Olšák2017-11-0247-195/+2
| | | | | | | It's inaccurate. Instead, see the copyright and use "git log" and "git blame" to know the authorship. Acked-by: Nicolai Hähnle <[email protected]>
* gallivm: allow arch rounding with avx512Tim Rowley2017-11-021-1/+2
| | | | | | Fixes piglit vs-roundeven-{float,vec[234]} with simd16 VS. Reviewed-by: Roland Scheidegger <[email protected]>
* etnaviv: Allow clearing constant buffer using buffer==NULL user_buffer==NULLWladimir J. van der Laan2017-11-021-1/+1
| | | | | | | | | Prevents an assertion when using GALLIUM_HUD with ioquake3, when cso_restore_constant_buffer_slot0 restores an empty constant buffer in slot 0. Signed-off-by: Wladimir J. van der Laan <[email protected]> Signed-off-by: Lucas Stach <[email protected]>
* etnaviv: Don't flush on transfer when UNSYNCHRONIZEDWladimir J. van der Laan2017-11-021-12/+12
| | | | | | | | | Structure code to only flush when we will potentially call cpu_prep. This prevents spurious flushes in applications that heavily rely on u_uploader. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Lucas Stach <[email protected]> Signed-off-by: Lucas Stach <[email protected]>
* etnaviv: don't do resolve-in-place without valid TSWladimir J. van der Laan2017-11-024-0/+11
| | | | | | | | | | | | GC3000 resolve-in-place assumes that the TS state is configured. If it is not, this will result in MMU errors. This is especially apparent when using glGenMipmaps(). Fixes: 78ade659569e ("etnaviv: Do GC3000 resolve-in-place when possible") Cc: [email protected] Signed-off-by: Wladimir J. van der Laan <[email protected]> Tested-by: Chris Healy <[email protected]> Signed-off-by: Lucas Stach <[email protected]>
* svga: Use __asm__ instead of asmDylan Baker2017-11-013-11/+5
| | | | | | | | | | | | __asm__ is portable, and allows the svga driver to be compiled with the c99 standard instead of requiring the gnu99 standard. I have compile tested this with GCC and Clang on Linux. Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Brian Paul <[email protected]> Tested-by: Brian Paul <[email protected]>
* Revert "winsys/amdgpu: Add R600_DEBUG flag to reserve VMID per ctx."Marek Olšák2017-11-016-15/+0
| | | | | | This reverts commit f03b7c9ad92c1656a221297819fbc6d065cc0af7. The libdrm interface is wrong.
* gallium: increase pipe_sampler_view::target bitfield size for MSVCBrian Paul2017-11-011-2/+6
| | | | | | | | | | | | | | | | | | MSVC treats enums as being signed. The 4-bit target field isn't large enough to correctly store the value 8 (for PIPE_TEXTURE_CUBE_ARRAY). The bitfield value 0x8 was being interpreted as -8 so matching the target with PIPE_TEXTURE_CUBE_ARRAY in switch statements, etc. was failing. To keep the structure size the same, we reduce the format field from 16 bits to 15. There don't appear to be any other enum bitfields which need to be adjusted. This fixes a number of Piglit cube map array tests. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* gallium: add cap for driver specified max combined shader resources.Dave Airlie2017-11-0118-1/+20
| | | | | | | | Some hw (evergreen) has a limit on how many combined (images/buffers/mrts) a fragment shader can access. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600/sb: bail out if prepare_alu_group() doesn't find a proper schedulingGert Wollny2017-11-012-20/+31
| | | | | | | | | | | | | | | It is possible that the optimizer ends up in an infinite loop in post_scheduler::schedule_alu(), because post_scheduler::prepare_alu_group() does not find a proper scheduling. This can be deducted from pending.count() being larger than zero and not getting smaller. This patch works around this problem by signalling this failure so that the optimizers bails out and the un-optimized shader is used. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103142 Cc: <[email protected]> Signed-off-by: Gert Wollny <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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