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* i915g: Make sure that new vbo gets updatedJakob Bornecrantz2010-12-022-5/+10
| | | | | | | | | Malloc likes to reuse old address as soon as possible this would cause the new vbo buffer to get the same address as the old. So make sure we set it to NULL when we allocate a new one. This fixes ipers which will fill up a couple of VBO buffers per frame. Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: Improve debug printing for texturesJakob Bornecrantz2010-12-021-4/+21
| | | | Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: Fix closure of full batch buffersChris Wilson2010-12-022-72/+30
| | | | | | | | Signed-off-by: Chris Wilson <[email protected]> [danvet: incorporate comments by Dr_Jakob] Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: track TODO itemsDaniel Vetter2010-12-021-0/+29
| | | | | | | | Just as a reminder for all things currently broken with i915g. Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: assert(depth_surface->offset == 0)Daniel Vetter2010-12-021-1/+2
| | | | | | | | Shouldn't happen and not supported, anyway. Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: enable x-tiling for render targetsDaniel Vetter2010-12-021-4/+0
| | | | | | Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: switch rendering to mipmapped textures to (x,y) offsetsDaniel Vetter2010-12-023-9/+29
| | | | | | | | | | | | | Byte offsets simply don't work with tiled render targets when using tiling bits. Luckily we can cox the hw into doing the right thing with the DRAWING_RECT command by disabling the drawing rect offset for the depth buffer. Minor fixes by Jakob Bornecrantz. Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: enable X-tiling for texturesDaniel Vetter2010-12-023-0/+27
| | | | | | | | | Tiling is rather fragile in general and results in pure blackness when unlucky. Hence add a new option to disable tiling. Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: don't pot-align stride for tiled buffersDaniel Vetter2010-12-021-2/+3
| | | | | | | | | libdrm will do this for us, if it's required (i.e. if tiling is possible). Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: postpone mipmap/face offset calculationDaniel Vetter2010-12-023-27/+43
| | | | | | | | | | | | | | | | | | | | libdrm-intel can refuse to tile buffers for various reasons. For potentially tiled buffers the stride is therefore only known after the iws->buffer_create_tiled call. Unconditionally rounding up to whatever tiling requires wastes space, so rework the code to not use tex->stride in the layout code. Luckily only the mimap/face offset calculation uses it which can easily be solved by storing an (x, y) coordinate pair. Furthermore this will be usefull later for properly supporting rendering into the different levels of tiled mipmap textures. v2: switch to nblocks(x|y): More in line with gallium and better suited for rendering into mipmap textures. Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: implement unfenced relocs for textures using tiling bitsDaniel Vetter2010-12-023-5/+20
| | | | | | Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: implement unfenced color&depth buffer using tiling bitsDaniel Vetter2010-12-022-8/+22
| | | | | | | | v2: Clarify tiling bit calculation as suggested by Chris Wilson. Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: return tiling in iws->buffer_from_handleDaniel Vetter2010-12-023-3/+9
| | | | | | | | | | This is needed to properly implement tiling flags. And the gem implemention fo buffer_from_handle already calls get_tiling, so it's for free. Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: prepare winsys/batchbuffer for execbuf2Daniel Vetter2010-12-028-27/+38
| | | | | | | | Wire up a fenced parameter, switch all relocations to _FENCED Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: switch to tiled allocations, kill set_fenceDaniel Vetter2010-12-024-60/+2
| | | | | | | | | This way relaxed fencing is handled by libdrm. And buffers _can't_ ever change their tiling. Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: add winsys function to create tiled buffersDaniel Vetter2010-12-024-14/+102
| | | | | | | | | | | | | | Different kernels have different restrictions for tiled buffers. Hence use the libdrm abstraction to calculate the necessary stride and height alignment requirements. Not yet used. v2: Incorporate review comments from Jakob Bornecrantz Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* i915g: drop alignment parameter from iws->buffer_createDaniel Vetter2010-12-026-21/+7
| | | | | | | | | | | | It's unnecessary. The kernel gem ignores it totally and we can't run on the old userspace fake bo manager due to lack of dri2. Also drop the redundant name string from the sw winsys as suggested by Jakob Bornecrantz Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Jakob Bornecrantz <[email protected]> Signed-off-by: Jakob Bornecrantz <[email protected]>
* r300g: disable ARB_texture_swizzle if S3TC is enabled on r3xx-onlyMarek Olšák2010-12-011-1/+2
| | | | | | r3xx cannot swizzle compressed textures. r4xx+ is unaffected. NOTE: This is a candidate for the 7.9 branch.
* r300g: fix texture swizzling with compressed textures on r400-r500Marek Olšák2010-12-017-13/+28
| | | | | | This fixes all S3TC piglit/texwrap tests. NOTE: This is a candidate for the 7.9 branch.
* r300/compiler: implement and lower OPCODE_CLAMPMarek Olšák2010-12-011-1/+1
| | | | Needed for st/vega.
* vega: Remove extraneous ;José Fonseca2010-12-011-1/+1
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* svga: Silence debug printf.José Fonseca2010-12-011-1/+0
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* st/vega: Avoid unnecessary constant bufer upload.Chia-I Wu2010-12-011-30/+48
| | | | Remember the last uploaded data and avoid re-uploading.
* st/vega: Initialize pipe states with renderer.Chia-I Wu2010-12-013-26/+28
| | | | | Initialize vertex elements, rasterizer, stencil ref, and vertex shader with renderer_create. Remove RASTERIZER_DIRTY and VS_DIRTY flags.
* st/vega: Create drawing surface mask as needed.Chia-I Wu2010-12-013-35/+38
| | | | | | | As the blend texture, a drawing surface mask is used when masking is enabled. It should be created as needed. s/alpha_mask/surface_mask/ to follow OpenVG 1.1 naming.
* st/vega: Delay blend texture creation until needed.Chia-I Wu2010-12-014-57/+32
| | | | | It is used for more advanced blending or mask update. It might not be ever needed for some applications.
* st/vega: Remove st_inlines.h.Chia-I Wu2010-12-015-127/+1
| | | | Per b0427bedde80e3189524651a327235bdfddbc613.
* st/vega: Simplify radial gradient.Chia-I Wu2010-12-011-73/+46
| | | | Eight less instructions with comments.
* st/vega: Fix degenerate paints.Chia-I Wu2010-12-016-9/+80
| | | | | Fix the case that the two points of a linear gradient coincide, or the case that the radius of a radial gradient is equal to or less than 0.
* st/vega: Fix negated logic in image_draw.Chia-I Wu2010-12-011-4/+4
| | | | A typo from last commit.
* st/vega: Fix paint coordinates transformations.Chia-I Wu2010-12-019-39/+94
| | | | | | | | Depending on whether vgDrawPath(mode), vgDrawImage, or vgDrawGlyph[s] is called, different paint-to-user and user-to-surface matrices should be used to derive the sample points for the paint. This fixes "paint" demo.
* st/vega: Bump version to 1.1.Chia-I Wu2010-12-011-2/+2
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* st/vega: Add color transformation support.Chia-I Wu2010-12-017-50/+123
| | | | | Per OpenVG 1.1. A new shader stage is added. It uses the first two constants of the fragment shader for color transformation parameters.
* st/vega: More flexible shader selection.Chia-I Wu2010-12-013-107/+130
| | | | | | | Divide bits of VegaShaderType into 6 groups: paint, image, mask, fill, premultiply, and bw. Each group represents a stage. At most one shader from each group will be selected when constructing the final fragment shader.
* st/vega: Revive mask layer support.Chia-I Wu2010-12-015-47/+64
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* st/vega: Add primitive text support.Chia-I Wu2010-12-015-80/+353
| | | | | | Optional features such as auth-hinting are not implemented. There is no anti-aliasing, and no effort is done to keep the glyph origin integral. So the text quality is poor.
* st/vega: Make image_draw take a matrix.Chia-I Wu2010-12-013-6/+4
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* st/vega: Make path_render and path_stroke take a matrix.Chia-I Wu2010-12-014-10/+10
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* st/vega: Fix image sampler views for alpha-only formats.Chia-I Wu2010-12-011-0/+7
| | | | For alpha-only VG formats, R = G = B = 1.0.
* st/vega: Update to latest headers.Chia-I Wu2010-12-012-9/+10
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* st/vega: Get rid of renderer_copy_texture.Chia-I Wu2010-12-014-78/+29
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* st/vega: vg_copy_texture and vg_copy_surface should share code.Chia-I Wu2010-12-011-44/+31
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* st/vega: Clean up renderer fields and functions.Chia-I Wu2010-12-012-108/+46
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* st/vega: Clean up vg_context fields and functions.Chia-I Wu2010-12-014-163/+9
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* st/vega: vg_manager should care about only the color buffer.Chia-I Wu2010-12-012-182/+184
| | | | | Move depth/stencil buffer, blend texture view, and alpha mask view creation to vg_context.c.
* st/vega: Make shader_bind call into the renderer.Chia-I Wu2010-12-013-31/+45
| | | | | | With this commit, the pipe states are entirely managed by the renderer. The rest of the code interfaces with the renderer instead of manipulating the states directly.
* st/vega: Move g3d states to renderer.Chia-I Wu2010-12-014-200/+230
| | | | | Let vg_context focus on OpenVG states and renderer focus on gallium states.
* st/vega: Use st_framebuffer for fb width/height.Chia-I Wu2010-12-014-30/+27
| | | | This allows us to eventually make g3d states opaque.
* st/vega: Delay fb state update to vg_validate_state.Chia-I Wu2010-12-013-64/+73
| | | | | | vg_manager_validate_framebuffer should mark the fb dirty and have vg_validate_state call cso_set_framebuffer. Rename VIEWPORT_DIRTY to FRAMEBUFFER_DIRTY.
* st/vega: Add POLYGON_STENCIL and POLYGON_FILL renderer state.Chia-I Wu2010-12-013-240/+277
| | | | | | The states are designated for polygon filling. Polygon filling is a two-pass process utilizing the stencil buffer. polygon_fill and polygon_array_fill functions are updated to make use of the state.
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