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* freedreno: drop unused arg from fd_batch_flush()Rob Clark2019-06-2612-23/+23
| | | | | | | The `force` arg has been unused for a while.. but apparently I forgot to garbage collect it. Signed-off-by: Rob Clark <[email protected]>
* panfrost/ci: Add RK3288 flipflops I don't want to deal with right nowAlyssa Rosenzweig2019-06-251-0/+6
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/ci: Update failures listAlyssa Rosenzweig2019-06-251-363/+3
| | | | | | | | A ton of tests were fixed by this series. A few were incorrectly passing before (QualityError, for instance) and now are explicitly failing. A few legitimate regressions but overwhelmingly positive. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/ci: Set MESA_GLES_VERSION_OVERRIDE=3.0Alyssa Rosenzweig2019-06-251-0/+1
| | | | | | | | Fixes cube map tests due to disagreements between Mesa, dEQP, and the spec... Signed-off-by: Alyssa Rosenzweig <[email protected]> Cc: Tomeu Vizoso <[email protected]>
* panfrost/ci: Run full set of mipmap testsAlyssa Rosenzweig2019-06-251-3/+0
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Advertise support for other 8-bit UNORM formatsAlyssa Rosenzweig2019-06-251-26/+15
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Use pipe_surface->format directly in blitterAlyssa Rosenzweig2019-06-251-1/+1
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Invert swizzle for renderingAlyssa Rosenzweig2019-06-251-2/+30
| | | | | | Fixes rendering to e.g. alpha textures. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Honour first_layer...last_layer when samplingAlyssa Rosenzweig2019-06-251-1/+3
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Use the sampler_view target (not the textures)Alyssa Rosenzweig2019-06-251-2/+2
| | | | | | | u_blitter gets "special treatment" and uses this mechanism to cast cube maps to 2D textures in order to texelFetch them. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Assert guard texelFetch against cubemapsAlyssa Rosenzweig2019-06-251-0/+3
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Zero pixels in any axis is zero pixels totalAlyssa Rosenzweig2019-06-251-1/+1
| | | | | | Multiplication, not addition, so switch the logic operator. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Respect mip level when wallpaperingAlyssa Rosenzweig2019-06-251-1/+7
| | | | | | | Fixes DATA_INVALID_FAULT raised when wallpapering while rendering to a mipmap. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Fixup NIR texture opAlyssa Rosenzweig2019-06-251-0/+8
| | | | | | | In a vertex shader, a tex op should map to txl, as there *must* be a LOD given to the hardware (implicitly or explicitly). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Support (non-)seamless cube mapsAlyssa Rosenzweig2019-06-253-4/+5
| | | | | | | Identify the seamless cubemap bit and passthrough the Gallium state rather than setting unconditionally. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Merge checksum buffer with main BOAlyssa Rosenzweig2019-06-255-47/+64
| | | | | | | | This is similar to the AFBC merge; now all (non-imported) buffers use a common backing buffer. Reenables checksumming, eliminating a performance regression. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/decode: Limit MRT blend countAlyssa Rosenzweig2019-06-251-3/+8
| | | | | | | I thought I already fixed this. Maybe that was a dream...? Then again, I might be dreaming now. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Clamp tile coordinates before job submissionAlyssa Rosenzweig2019-06-251-0/+20
| | | | | | | Fixes TILE_RANGE_FAULT raised on some tests in dEQP-GLES3.functional.fbo.blit.* Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Use dedicated u_blitter context for wallpapersAlyssa Rosenzweig2019-06-253-19/+35
| | | | | | | | | | The main ctx->blitter instance should be reserved for blits originated from Gallium (like mipmap generation). Since wallpapering is conceptually different -- wallpaper blits can be triggered by Gallium blits -- the blitter pipes must be separate to avoid potential u_blitter recursion. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Sanity check layerAlyssa Rosenzweig2019-06-251-0/+1
| | | | | | | It doesn't make sense to try to render to multiple array elements at once. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Divide array_size by 6 for cubemapsAlyssa Rosenzweig2019-06-251-0/+1
| | | | | | | Addresses the disparity between Mali and Gallium definitions of array_size. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Use get_texture_address for framebuffer computationsAlyssa Rosenzweig2019-06-254-25/+28
| | | | | | | Allows for sharing some code as well as theoretically allowing cubemap rendering. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Merge AFBC slab with BO backingAlyssa Rosenzweig2019-06-255-91/+46
| | | | | | | | | | | | | | | Rather than tracking AFBC memory "specially", just use the same codepath as linear and tiled. Less things to mess up, I figure. This allows us to use the standard setup_slices() call with AFBC resources, allowing mipmapped AFBC resources. Unfortunately, we do have to disable AFBC (and checksumming) in the meantime to avoid functional regressions, as we don't know _a priori_ if we'll need to access a resource from software (which is not yet hooked up with AFBC) and we don't yet have routines to switch the layout of a BO at runtime. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Z/S can't be tiledAlyssa Rosenzweig2019-06-251-0/+3
| | | | | | | | As far as we know, Utgard-style tiling only works for color render targets, not depth/stencil, so ensure we don't try to tile it (rather than compress or plain old linear) and drive ourselves into a corner. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Enable mipmappingAlyssa Rosenzweig2019-06-251-1/+1
| | | | | | | Now the autogeneration of mipmaps is working (via u_blitter), we can finally enable mipmaps! Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Enable blittingAlyssa Rosenzweig2019-06-251-4/+0
| | | | | | | Now that all the prerequisites breaking u_blitter are fixed, we can finally hook up panfrost_blit. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Allow texelFetch for wallpaper blitsAlyssa Rosenzweig2019-06-251-3/+1
| | | | | | We just implemented the routine; we may as well use it. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Implement texelFetch (2D only)Alyssa Rosenzweig2019-06-251-6/+35
| | | | | | | | txf instructions can result from blits, so handle them rather than crash. Only works for 2D textures (not even 2D array texture) due to a register allocation constraint that may not be sorted for a while. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Skip flushes only for wallpapers, not any blitAlyssa Rosenzweig2019-06-251-1/+1
| | | | | | | We need the flush from u_blitter for a normal blit (e.g. for mipmaps); it's only wallpaper-related blits that are special-cased. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Handle generate_mipmap ourselvesAlyssa Rosenzweig2019-06-252-0/+55
| | | | | | | | | | | | | To avoid interference with the wallpaper code, we need to do some state tracking when generating mipmaps. In particular, we need to mark the generated layers as invalid before generating the mipmap, so we don't try to backblit them if they already had content. Likewise, we need to flush both before and after generating a mipmap since our usual set_framebuffer_state flushing isn't quite there yet. Ideally better optimizations would save the flush but I digress. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Disable mipmapping if necessaryAlyssa Rosenzweig2019-06-251-0/+16
| | | | | | | | If a mipfilter is not set, it's legal to have an incomplete mipmap; we should handle this accordingly. An "easy way out" is to rig the LOD clamps. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* virgl: add VIRGL_DEBUG_XFERChia-I Wu2019-06-253-4/+9
| | | | | | | | When set, do as requested and skip any transfer optimization. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-By: Gert Wollny <[email protected]> Reviewed-By: Alexandros Frantzis <[email protected]>
* virgl: add VIRGL_DEBUG_SYNCChia-I Wu2019-06-253-1/+20
| | | | | | | | When set, wait after every each flush. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-By: Gert Wollny <[email protected]> Reviewed-By: Alexandros Frantzis <[email protected]>
* virgl: fix the value of VIRGL_DEBUG_BGRA_DEST_SWIZZLEChia-I Wu2019-06-252-8/+10
| | | | | | | | | | | | VIRGL_DEBUG_BGRA_DEST_SWIZZLE should use bit 3. Make some cosmetic changes as well. Fixes: a478e56fbd33fa23503b63d41265a1c2f3253ed2 virgl: Add debug flag to bypass driconf to enable the BGRA tweaks Signed-off-by: Chia-I Wu <[email protected]> Reviewed-By: Gert Wollny <[email protected]> Reviewed-By: Alexandros Frantzis <[email protected]>
* freedreno/a5xx: fix batch leak in fd5 blitter pathRob Clark2019-06-241-0/+1
| | | | | Fixes: 3d198926a48 freedreno: use fd_bc_alloc_batch instead of fd_batch_create. Signed-off-by: Rob Clark <[email protected]>
* radeonsi: don't set spi_ps_input_* for monolithic shadersMarek Olšák2019-06-241-13/+26
| | | | | | | | The driver doesn't use these values and ac_rtld has assertions expecting the value of 0. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: rename and re-document cache flush flagsMarek Olšák2019-06-2410-64/+66
| | | | | | | SMEM and VMEM caches are L0 on gfx10. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: fix AMD_DEBUG=nofmaskMarek Olšák2019-06-244-14/+20
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radeonsi: flatten the switch for DPBB tunablesMarek Olšák2019-06-241-14/+4
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: set the calling convention for inlined function callsMarek Olšák2019-06-242-2/+2
| | | | | | | otherwise the behavior is undefined Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: refactor si_update_vgt_shader_configNicolai Hähnle2019-06-242-28/+60
| | | | | | | | | | We'll have to extend this at some point, and using a bitfield union in this way makes it easier to get the right index without excessive branching. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* freedreno: Stop treating UBO 0 specially in UBO uploading.Eric Anholt2019-06-241-33/+1
| | | | | | | | | ir3_nir_analyze_ubo_ranges() has already told us how much of cb0 we need to upload (all of it, since it will lower indirect UBO 0 accesses from load_ubo back to indirection on the constant buffer). Reviewed-by: Kristian H. Kristensen <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno: Clamp UBO uploads to the constlen decided by the shader.Rob Clark2019-06-241-0/+11
| | | | | | | | | | | | If the NIR-level analysis decided to move UBO loads to the constant file, but the backend decided not to load those constants, we could upload past the end of constlen. This is particularly relevant for pre-a6xx, where we emit a different constlen between bin and render variants. (Fix by Rob, commit message by anholt) Reviewed-by: Eric Anholt <[email protected]>
* panfrost: Allow up to 16 UBOsAlyssa Rosenzweig2019-06-241-1/+1
| | | | | | This is the hardware max, as far as I can tell. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: DRY between shader stage setupAlyssa Rosenzweig2019-06-241-19/+36
| | | | | | | Just a little spring cleanup, extending UBOs to vertex shaders in the process. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Implement UBO readsAlyssa Rosenzweig2019-06-241-14/+51
| | | | | | | UBOs and uniforms now use a common code path with an explicit `index` argument passed, enabling UBO reads. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Handle disabled/empty UBOsAlyssa Rosenzweig2019-06-241-1/+13
| | | | | | | Prevents an assert(0) later in this (not so edge) case. We still have to have a dummy there. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Identify "uniform buffer count" bitsAlyssa Rosenzweig2019-06-243-22/+21
| | | | | | | We've known about this for a while, but it was never formally in the machine header files / decoder, so let's add them in. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Upload UBOsAlyssa Rosenzweig2019-06-241-0/+31
| | | | | | | Now that all the counting is sorted, it's a matter of passing along a GPU address and going. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Allow for dynamic UBO countAlyssa Rosenzweig2019-06-241-11/+16
| | | | | | | We already uploaded UBOs, but only a fixed number (1) for uniforms; let's upload as many as we compute we need. Signed-off-by: Alyssa Rosenzweig <[email protected]>
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