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* radeonsi/gfx10: implement si_shader_psNicolai Hähnle2019-07-031-7/+13
* radeonsi/gfx10: generate VS and TES as NGG merged ESGS shadersNicolai Hähnle2019-07-036-25/+382
* radeonsi/gfx10: distinguish between merged shaders and multi-part shadersNicolai Hähnle2019-07-031-3/+10
* radeonsi/gfx10: update si_get_shader_nameNicolai Hähnle2019-07-031-0/+4
* radeonsi/gfx10: add as_ngg shader key bitNicolai Hähnle2019-07-033-10/+42
* radeonsi/gfx10: implement si_update_shadersNicolai Hähnle2019-07-031-50/+62
* radeonsi/gfx10: implement si_build_vgt_shader_configNicolai Hähnle2019-07-032-2/+14
* radeonsi/gfx10: keep track of whether NGG is usedNicolai Hähnle2019-07-034-1/+31
* radeonsi/gfx10: document NGG shader stagesNicolai Hähnle2019-07-031-10/+15
* radeonsi/gfx10: implement gfx10_emit_cache_flushNicolai Hähnle2019-07-034-3/+195
* radeonsi/gfx10: add si_context::emit_cache_flushNicolai Hähnle2019-07-039-9/+15
* radeonsi/gfx10: implement DB registersNicolai Hähnle2019-07-033-13/+56
* radeonsi/gfx10: set CB registersNicolai Hähnle2019-07-032-5/+76
* radeonsi/gfx10: always set up sample locationsNicolai Hähnle2019-07-031-1/+5
* radeonsi/gfx10: use Z32_FLOAT_CLAMP for upgraded depth texturesNicolai Hähnle2019-07-032-10/+22
* radeonsi/gfx10: implement vertex format changesNicolai Hähnle2019-07-032-6/+23
* radeonsi/gfx10: implement si_set_{constant,shader}_bufferNicolai Hähnle2019-07-031-6/+20
* radeonsi/gfx10: implement si_make_buffer_descriptorNicolai Hähnle2019-07-031-10/+28
* radeonsi/gfx10: implement si_set_mutable_tex_desc_fieldsNicolai Hähnle2019-07-031-5/+30
* radeonsi/gfx10: gfx10 can render up to 8192 layersNicolai Hähnle2019-07-031-0/+4
* radeonsi/gfx10: add gfx10_make_texture_descriptorNicolai Hähnle2019-07-031-1/+187
* radeonsi/gfx10: add pipe_screen::make_texture_descriptorNicolai Hähnle2019-07-035-16/+19
* radeonsi/gfx10: determine view->is_integer based on the pipe_formatNicolai Hähnle2019-07-031-6/+15
* radeonsi/gfx10: implement si_is_format_supportedNicolai Hähnle2019-07-031-0/+17
* radeonsi/gfx10: generate gfx10_format_table.hNicolai Hähnle2019-07-035-2/+300
* radeonsi/gfx10: set MAX_ALLOC_COUNTNicolai Hähnle2019-07-031-2/+14
* radeonsi/gfx10: require LLVM 9Nicolai Hähnle2019-07-031-0/+6
* radeon/vcn: update for new vcn enc interfaceBoyuan Zhang2019-07-032-1/+4
* radeonsi: enable jpeg decode for navi10Boyuan Zhang2019-07-031-1/+2
* radeon/vcn: implement vcn 2.0 jpeg decodeBoyuan Zhang2019-07-031-56/+157
* radeon/vcn: add direct register boolBoyuan Zhang2019-07-032-0/+3
* radeon/vcn: add defines for vcn 2.0 jpegBoyuan Zhang2019-07-031-0/+25
* radeon/vcn: use variable to assign ib cmdBoyuan Zhang2019-07-033-40/+128
* radeon/vcn: implement vcn 2.0 encodeBoyuan Zhang2019-07-034-5/+220
* radeon/vcn: add vcn2.0 encode skeletonBoyuan Zhang2019-07-034-0/+81
* radeon/vcn: move vcn1.0 specific defines to cBoyuan Zhang2019-07-032-29/+29
* radeon/vcn: assign function pointer with ib functionsBoyuan Zhang2019-07-033-165/+182
* radeon/vcn: add function pointer for ib functionsBoyuan Zhang2019-07-031-0/+32
* radeon/vcn: move header related algorithm to vcn_encBoyuan Zhang2019-07-033-122/+142
* radeon/vcn: move add buf func to common fileBoyuan Zhang2019-07-033-16/+17
* radeon/vcn: move cs defines to enc header fileBoyuan Zhang2019-07-032-10/+10
* radeon/vcn: add VP9 support for Navi10Leo Liu2019-07-031-10/+20
* radeonsi: enable encode support for newer HWLeo Liu2019-07-031-5/+3
* radeon/vcn: add VCN2 set of internal registers for IBLeo Liu2019-07-032-9/+31
* radeonsi/uvd: allow newer HW to create HW decoderLeo Liu2019-07-031-2/+1
* amd/common/gfx10: add register JSONNicolai Hähnle2019-07-033-6/+6
* amd/common: add GFX10 chipsNicolai Hähnle2019-07-031-1/+3
* radeonsi: make emit_streamout_output externally accessibleNicolai Hähnle2019-07-032-7/+12
* radeonsi: pass the context to query destroy functionsNicolai Hähnle2019-07-033-11/+10
* radeonsi: make si_restore_qbo_state externally availableNicolai Hähnle2019-07-033-14/+14
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