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* radeonsi: enable OpenGL 3.3 compat profileTimothy Arceri2018-06-191-1/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* v3d: Set the SO offsets correctly if we have to re-emit.Eric Anholt2018-06-185-4/+24
| | | | | | This should fix TF across a glFlush() or TF pause/restart. Fixes dEQP-GLES3.functional.transform_feedback.array.interleaved.lines.highp_float and many, many others.
* gallium/hud: = should rename the last added data sourceMarek Olšák2018-06-181-1/+4
| | | | Tested-by: Dieter Nützel <[email protected]>
* swr/rast: Clang-Format most rasterizer source codeAlok Hota2018-06-18114-22174/+27802
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* mesa: Unconditionally enable floating-point texturesTimothy Arceri2018-06-181-9/+0
| | | | | | | | | | | | | | ARB_texture_float references US Patent #6,650,327 [1] which has a filing date of June 16 1998. According to [2], patents filed after 1995 expire 20 years from the filing date, giving an expiration of June 17 2018. [1] https://www.google.com/patents/US6650327 [2] https://en.wikipedia.org/wiki/Term_of_patent_in_the_United_States Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* v3d: Handle a no-intersection scissor even if it's outside of the VP.Eric Anholt2018-06-151-10/+8
| | | | | | The min/maxes ended up producing a negative clip width/height for dEQP-GLES3.functional.fragment_ops.scissor.outside_render_line. Just make sure they stay at 0 (or v3d 3.x's workaround) if that happens.
* v3d: Use the proper depth texture type for sampling.Eric Anholt2018-06-151-3/+3
| | | | Fixes failing tests in dEQP-GLES3.functional.texture.shadow
* v3d: Fix shaders using pixel center W but no varyings.Eric Anholt2018-06-151-1/+1
| | | | | | | | The docs called this field "uses both center W and centroid W", but actually it's "do you need center W even if varyings don't obviously call for it?" Fixes dEQP-GLES3.functional.shaders.builtin_variable.fragcoord_w
* nvc0: add support for programmable sample locationsRhys Perry2018-06-1410-46/+299
| | | | Signed-off-by: Rhys Perry <[email protected]>
* gallium: add support for programmable sample locationsRhys Perry2018-06-1424-2/+120
| | | | | | Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Brian Paul <[email protected]> (v2) Reviewed-by: Marek Olšák <[email protected]> (v2)
* v3d: Fix polygon offset for Z16 buffers.Eric Anholt2018-06-143-2/+14
| | | | | | Fixes: dEQP-GLES3.functional.polygon_offset.fixed16_displacement_with_units dEQP-GLES3.functional.polygon_offset.fixed16_render_with_units
* v3d: Don't set the first_ez_state to DISABLED if after only UNDECIDED draws.Eric Anholt2018-06-141-1/+2
| | | | | | | | | We need to have the RCL start with EZ enabled, since those undecided draws had EZ enabled. But we do need to update from UNDECIDED to LT or GT as necessary still. Fixes many simulator assertion fails in deqp fragment_ops/interaction/basic_shader/*
* v3d: Use the right size for v3d 4.x TEXTURE_SHADER_STATE BO.Eric Anholt2018-06-141-2/+2
| | | | This doesn't really matter, since they both get rounded up to 4096.
* v3d: Add static asserts for other packed packet sizes.Eric Anholt2018-06-142-0/+7
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* v3d: Fix the size of the packed attribute state.Eric Anholt2018-06-141-1/+1
| | | | Fixes segfaults in dEQP-GLES3.functional.vertex_array_objects.all_attributes.
* v3d: Remove some unused context fields from vc4.Eric Anholt2018-06-141-11/+0
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* v3d: Remove unused QUNIFORM_STENCIL left over from vc4.Eric Anholt2018-06-141-9/+0
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* v3d: Use our #define for max attributes in shader caps.Eric Anholt2018-06-141-1/+1
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* meson: only build vl_winsys_dri.c when x11 platform is usedLukas Rusak2018-06-141-1/+1
| | | | | | | | | | | | | | This seems to have been missed in the move from autotools This fixes the following build issue: ../src/gallium/auxiliary/vl/vl_winsys_dri.c:34:10: fatal error: X11/Xlib-xcb.h: No such file or directory #include <X11/Xlib-xcb.h> ^~~~~~~~~~~~~~~~ Fixes: b1b65397d0c4978e36a84c0a1c98a4bd6cb9588e ("meson: Build gallium auxiliary") Reviewed-by: Dylan Baker <[email protected]>
* radeonsi/gfx9: fix si_get_buffer_from_descriptors for 48-bit pointersMarek Olšák2018-06-131-2/+2
| | | | | | | | This fixes: GL45-CTS.pipeline_statistics_query_tests_ARB.functional_compute_shader_invocations Cc: 18.0 18.1 <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi/gfx9: update & clean up a DPBB heuristicMarek Olšák2018-06-131-9/+5
| | | | Tested-by: Dieter Nützel <[email protected]>
* radeonsi/gfx9: set POPS_DRAIN_PS_ON_OVERLAP due to a hw bugMarek Olšák2018-06-131-2/+4
| | | | | | This may not be needed yet, but let's set it now. Tested-by: Dieter Nützel <[email protected]>
* radeonsi/gfx9: remove UINT_MAX array terminators in bin size tablesMarek Olšák2018-06-131-19/+1
| | | | Tested-by: Dieter Nützel <[email protected]>
* radeonsi/gfx9: update bin sizesMarek Olšák2018-06-131-35/+38
| | | | | | This is based on our docs (recently updated), not amdvlk. Tested-by: Dieter Nützel <[email protected]>
* radeonsi/gfx9: update primitive binning code for EQAAMarek Olšák2018-06-131-4/+9
| | | | Tested-by: Dieter Nützel <[email protected]>
* radeonsi: assume that rasterizer state is non-NULL in draw_vboMarek Olšák2018-06-134-75/+61
| | | | Tested-by: Dieter Nützel <[email protected]>
* radeonsi: micro-optimize prim checking and fix guardband with lines+adjacencyMarek Olšák2018-06-134-13/+23
| | | | Tested-by: Dieter Nützel <[email protected]>
* radeonsi: move the guardband registers into a separate state atomMarek Olšák2018-06-135-19/+35
| | | | | | | | | They have a different frequency of updates and don't change when scissors change. I think this even fixes something in si_update_vs_viewport_state. Tested-by: Dieter Nützel <[email protected]>
* radeonsi/gfx9: implement the scissor bug workaround without performance dropMarek Olšák2018-06-132-29/+81
| | | | | | This might improve performance on Vega10 and Raven. Tested-by: Dieter Nützel <[email protected]>
* radeonsi: don't set VGT_LS_HS_CONFIG if it doesn't changeMarek Olšák2018-06-133-6/+12
| | | | Tested-by: Dieter Nützel <[email protected]>
* radeonsi: move VGT_GS_OUT_PRIM_TYPE into si_shader_gsMarek Olšák2018-06-134-33/+26
| | | | | | same as amdvlk. Tested-by: Dieter Nützel <[email protected]>
* radeonsi: record CLIPVERTEX output usage properly for compatibility profilesMarek Olšák2018-06-131-1/+0
| | | | | | This was missed when adding CLIPVERTEX support into GS & tess. Tested-by: Dieter Nützel <[email protected]>
* radeonsi: fix FBFETCH with 2D MSAA arraysMarek Olšák2018-06-131-1/+2
| | | | Tested-by: Dieter Nützel <[email protected]>
* radeonsi: return real memory usage instead of per-process usageMarek Olšák2018-06-131-2/+2
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* virgl: add ARB_tessellation_shader support. (v2)Dave Airlie2018-06-147-8/+107
| | | | | | | | | | This should add all the pieces to enable tess shaders on virgl. v2: fixup transform to handle tess and strip out precise. set default for max patch varyings to work around issue when tess gets enabled from v1 caps but v2 caps aren't in place. (Elie) Reviewed-by: Elie Tournier <[email protected]>
* freedreno/ir3: use pipe_image_view's cppRob Clark2018-06-111-1/+6
| | | | | | | At least for PIPE_BUFFER, we could get the resource used as (for example) R32F imageBuffer. So using cpp=1 from the rsc is wrong. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix image dimensions offsetRob Clark2018-06-111-1/+1
| | | | | | copy-pasta fail from how SSBO sizes are handled. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: correct image/ssbo offsetRob Clark2018-06-111-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: use saml always if we have lodRob Clark2018-06-111-1/+1
| | | | | | | In some cases we get plain tex opcodes (but w/ a lod argument).. in this case always use the saml instruction. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: don't cp absneg into meta:fiRob Clark2018-06-111-0/+4
| | | | | | | | | | | If using a fanin (collect) to collect of consecutive registers together, we can CP mov's into the fanin, but not (abs) or (neg). No places that allow those modifiers are consuming a fanin anyways. But this caused an absneg to be lost between a ldgb and stgb for shaders like: outputs[n] = abs(input[n]) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: rework size/type conversion instructionsRob Clark2018-06-111-10/+156
| | | | | | With 8b and 16b, there are a lot more to handle. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: propagate HALF flag across fanoutRob Clark2018-06-111-1/+4
| | | | | | | | | | If we have a fanout (split) meta instruction to split the result of a vector instruction, propagate the HALF flag back to the original instruction. Otherwise result ends up in a full precision register while instruction(s) that use the result look in a half-precision register. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: add sample-id/sample-mask-inRob Clark2018-06-111-3/+12
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add sample-id/sample-mask-inRob Clark2018-06-111-0/+21
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2018-06-118-87/+213
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: image atomics use image-store pathRob Clark2018-06-111-0/+8
| | | | | | | | image reads are handled via tex state, whereas image writes and atomics are handled via SSBO state block. Previously we were only considering image write, and not image atomics which also uses the SSBO state block. Signed-off-by: Rob Clark <[email protected]>
* virgl: enable ARB_gpu_shader_fp64Dave Airlie2018-06-111-1/+2
| | | | | | | This enables ARB_gpu_shader_fp64 if the host provides it. Tested-by: Gurchetan Singh <[email protected]> Reviewed-by: Gurchetan Singh <[email protected]>
* radeonsi: emit_dpbb_state packets optimizationSonny Jiang2018-06-072-21/+26
| | | | | | | Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: emit_clip_state packets optimizationSonny Jiang2018-06-072-3/+7
| | | | | | | Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: emit_msaa_sample_locs packets optimizationSonny Jiang2018-06-072-2/+6
| | | | | | | Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG packets Signed-off-by: Sonny Jiang <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
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